ADPA7009CHIP datasheet(18/28 Pages) AD

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ADPA7009CHIP

Data Sheet

Rev. 0 | Page 18 of 28

THEORY OF OPERATION

The architecture of the ADPA7009CHIP, a medium power

amplifier, is shown in Figure 65. The ADPA7009CHIP uses a

cascaded, four-stage amplifier operating in quadrature between

two 90° hybrids.

The input signal is divided evenly in two. Each path is amplified

through four independent gain stages. The amplified signals are

then combined at the output. This balanced amplifier approach

forms an amplifier with a combined gain of 19.5 dB and a PSAT

value of 29 dBm. The gate pins are internally connected and

can be biased from either north or south of the circuit.

A portion of the RF output signal is directionally coupled to a

diode for detection of the RF output power. When the diode is

dc biased, the diode rectifies the RF power and makes the RF

power available for measurement as a dc voltage at VDET. To

allow temperature compensation of VDET, an identical and

symmetrically located circuit, minus the coupled RF power, is

available via VREF. Taking the difference of VREF − VDET

provides a temperature compensated signal that is proportional

to the RF output (see Figure 65).

VDD2 VDD4

RFOUT

VREF

DIRECTIONAL

COUPLER

VGG1 VGG2

VDD1

VDD3

RFIN

VDET

Figure 65. ADPA7009CHIP Architecture

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