ADPA7009CHIP datasheet(23/28 Pages) AD

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Data Sheet

ADPA7009CHIP

Rev. 0 | Page 23 of 28

HMC980LP4E BIAS SEQUENCE

The dc supply sequence described in this section is required to

prevent damage to the HMC980LP4E when using the device to

control the ADPA7009CHIP.

Power-Up Sequence

The power-up sequence for the HMC980LP4E is as follows:

1. Set VDIG = 3.3 V.

2. Set S0 = 3.3 V.

3. Set VDD = 5.72 V.

4. Set VNEG = −1.5 V (this step is unnecessary if using an

internally generated voltage).

5. Set EN = 3.3 V (the transition from 0 V to 3.3 V turns on

VGATE and VDRAIN).

Power-Down Sequence

The power-down sequence for the HMC980LP4E is as follows:

1. Set EN = 0 V (the transition from 3.3 V to 0 V turns off

VDRAIN and VGATE).

2. Set VNEG = 0 V (this step is unnecessary if using and

internally generated voltage).

3. Set VDD = 0 V.

4. Set S0 = 0 V.

5. Set VDIG = 0 V.

After the HMC980LP4E bias control circuit is set up, toggle

the bias to the ADPA7009CHIP on or off by applying 3.3 V or

0 V, respectively, to the EN pad. At EN = +3.3 V, VGATE drops to

−1.5 V, and VDRAIN turns on at +5 V. VGATE then rises until

IDRAIN = 850 mA, and the closed control loop regulates IDRAIN at

850 mA. When EN = 0 V, VDRAIN is set to −1.5 V, and

VDRAIN is set to 0 V.

CONSTANT DRAIN CURRENT BIASING vs.

CONSTANT GATE VOLTAGE BIASING

The HMC980LP4E uses closed-loop feedback to continuously

adjust VGATE to maintain a constant drain current bias over

dc supply variation, temperature, and device to device

variation. In addition, constant drain current bias is the

optimum method for reducing time in calibration procedures

and for maintaining consistent performance over time. By

comparing the constant drain current bias with a constant gate

voltage bias where the current is driven to increase when RF power

is applied, a slightly lower output P1dB is seen with a constant

drain current bias. This output P1dB is shown in Figure 78, where

the RF performance is slightly lower than the constant gate

voltage bias operation due to a lower drain current at the high

input powers as the device reaches 1 dB compression.

To increase the output P1dB performance for the constant

drain current bias toward the constant gate voltage bias

performance, increase the set current toward the IDD value this

performance reaches under the RF drive in the constant gate

voltage bias condition, as shown in Figure 78. The limit of

increasing IDQ under the constant drain current operation is set by

the thermal limitations found in Table 5 with the maximum

power dissipation specification. As the IDD increase continues,

the actual output P1dB does not continue to increase indefinitely

and the power dissipation increases. Therefore, when using

constant drain current biasing, take the trade-off between the

power dissipation and the output P1dB performance into

consideration.

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