ADRF5024

Data Sheet

Rev. C | Page 10 of 13

APPLICATIONS INFORMATION

EVALUATION BOARD

The ADRF5024-EVALZ is a 4-layer evaluation board. The

outer copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz

(2.2 mil) and are separated by dielectric materials. Figure 17

shows the evaluation board stackup.

0.5oz Cu (0.7mil)

RO4003

0.5oz Cu (0.7mil)

1.5oz Cu (2.2mil)

1.5oz Cu (2.2mil)

W = 14mil

G = 7mil

T = 2.2mil

H = 8mil

1.5oz Cu (2.2mil)

1.5oz Cu (2.2mil)

Figure 17. Evaluation Board (Cross Section View)

All RF and dc traces are routed on the top copper layer,

whereas the inner and bottom layers are grounded planes that

provide a solid ground for the RF transmission lines. The top

dielectric material is 8 mil Rogers RO4003, offering optimal

high frequency performance. The middle and bottom dielectric

materials provide mechanical strength. The overall board

thickness is 62 mil, which allows 2.4 mm RF launchers to

be connected at the board edges.

WITHOUT

IMPEDANCE

MATCH

WITH

IMPEDANCE

MATCH

Figure 18. Evaluation Board Layout, Top View

The RF transmission lines were designed using a coplanar

waveguide (CPWG) model, with trace width of 14 mil and

ground clearance of 7 mil to have a characteristic impedance of

50 Ω. For optimal RF and thermal grounding, as many plated

through vias as possible are arranged around transmission lines

and under the exposed pad of the package.

The ADRF5024-EVALZ has two layouts implemented, with

and without impedance matching. By default, the impedance

matched circuit is populated. For more details on this impedance

matched circuit, refer to Impedance Matching in the Probe

Matrix Board section.

THRU CAL can be used to calibrate out the board loss effects

from the ADRF5024-EVALZ evaluation board measurements

to determine the device performance at the pins of the IC.

Figure 19 shows the typical board loss for the ADRF5024-

EVALZ evaluation board at room temperature, the embedded

insertion loss, and the de-embedded insertion loss for the

ADRF5024.

–7

–6

–5

–4

–3

–2

–1

0

0

5

10

15

20

25

30

35

40

45

50

FREQUENCY (GHz)

THRU LOSS

EMBEDDED INSERTION LOSS

DEEMBEDDED INSERTION LOSS

Figure 19. Insertion Loss vs. Frequency

Figure 20 shows the actual ADRF5024-EVALZ with its

component placement.

Two power supply ports are connected to the VDD and VSS

test points, TP7 and TP5 (or TP3 and TP1 if using without

impedance match circuit), and the ground reference is

connected to the GND test point, TP4 or TP8. On the supply

traces, VDD and VSS, a 100 pF bypass capacitor filters high

frequency noise. Additionally, unpopulated components

positions are available for applying extra bypass capacitors.

A control port is connected to the CTRL test point, TP6 (or

TP2 for without impedance match circuit). There are

provisions for the resistor capacitor (RC) filter to eliminate dc-

coupled noise, if needed, by the application. The resistor can

also improve the isolation between the RF and the control

signal.

The RF input and output ports (RFC, RF1, and RF2) are

connected through 50 Ω transmission lines to the 2.4 mm

RF launchers, J10, J9, and J8 (or J2, J3, and J1 for without

impedance match circuit), respectively. These high frequency

RF launchers are by contact and are not soldered to the board.

A THRU CAL line connects the unpopulated J6 and J7

launchers (or J4 and J5 for without impedance match circuit).

This transmission line is used to estimate the loss due to the

PCB over the environmental conditions being evaluated.

The schematic of the ADRF5024-EVALZ evaluation board

is shown in Figure 21.