AVO=Gm∙RO

(14)

fPLF= 1

2∙π∙RO∙CC

(15)

fPHF= 1

2∙π∙RO∙CO

(16)

Whereas the zero is defined as:

fZ= 1

2∙π∙RC∙CC

(17)

7.3

Voltage divider

(18)

A small signal capacitor in parallel to the upper resistor (only for the adjustable part number) of the voltage divider

(*) Synchronization is allowed for LNM versions only.

Laplace transformer of the leading network:

GDIVs = R2R1+R2∙ 1+s∙R1∙CR1

1+s∙ R1∙R2

R1+R2∙CR1

(19)

fZ= 1

2∙π∙R1∙CR1

(20)

fP= 1

2∙π∙ R1∙R2

R1+R2∙CR1

(21)

fZ<fP

(22)

So closing the loop, the loop gain is:

Gs =GDIVs ∙GCOs ∙AOs

(23)

L6982

Voltage divider

DS13683 - Rev 1

page 23/48