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L6982 数据表(PDF) 3 Page - STMicroelectronics |
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L6982 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 48 page ![]() 2 Pin configuration Figure 2. Pin connection (top view) 1 2 3 4 8 7 6 5 SW BOOT VCC FB/VOUT EN/CLKIN(*) AGND VIN PGND (*) Synchronization is allowed for LNM versions only. Table 1. Pin description Pin # Symbol Function 1 SW Switching node. 2 BOOT Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The gate charge required to drive the internal NMOS is refreshed during the low side switch conduction time. 3 VCC This pin supplies the embedded analog circuitry. Connect a ceramic capacitor (≥ 1 µF) to filter internal voltage reference. 4 FB/VOUT FB is output voltage sensing with eternal voltage divider. 5 EN/CLKIN Enable pin with internal voltage divider. Pull down/up to disable/enable the device. In LNM versions, this pin is also used to provide an external clock signal, which synchronizes the device. 6 AGND Analog ground. 7 VIN DC input voltage. 8 PGND Power ground. L6982 Pin configuration DS13683 - Rev 1 page 3/48 |
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