ADRF6780ACPZN-R7 datasheet(31/35 Pages) AD

31 / 35 page

Data Sheet

ADRF6780

Rev. D | Page 31 of 35

ADC_CONTROL REGISTER

Address: 0x06, Reset: 0x0000, Name: ADC_CONTROL

ADC Clock Enable

1: Enable.

0: Disable.

VDET Output Pin Select

1: VDET Output Select Enable.

0: VDET Output Select Disable.

ADC Enable and Com parator on

1: Enable.

0: Disable.

ADC FallEdge to Start ADCConversion-Write

High Then Low

1: Set ADC conversion control high.

edge.

ADC conversion activated at falling

[15:4] RESERVED

[0] ADC_CLOCK_ENABLE (R/W)

[3] VDET_OUTPUT_SELECT (R/W)

[1] ADC_ENABLE (R/W)

[2] ADC_START (R/W)

Table 14. Bit Descriptions for ADC_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

[15:4]

RESERVED

Reserved

0x0

R/W

VDET_OUTPUT_SELECT

VDET Output Pin Select

0x0

R/W

VDET Output Select Disable

VDET Output Select Enable

ADC_START

ADC Fall Edge to Start ADC Conversion Write High Then Low

0x0

R/W

ADC Conversion Activated at Falling Edge

Set ADC conversion control High

ADC_ENABLE

ADC Enable and Comparator On

0x0

R/W

Disable

Enable

ADC_CLOCK_ENABLE

ADC Clock Enable

0x0

R/W

Disable

Enable

ADC_OUTPUT REGISTER

Address: 0x0C, Reset: 0x0010, Name: ADC_OUTPUT

Detector ADC 8 Bit Output

ADC Busy

1: Ready.

0: Bus y.

[15:9] RESERVED

[7:0] ADC_VALUE (R)

[8] ADC_STATUS (R)

Table 15. Bit Descriptions for ADC_OUTPUT

Bits

Bit Name

Settings

Description

Reset

Access

[15:9]

RESERVED

Reserved

0x0

R/W

ADC_STATUS

ADC Busy

0x0

Busy

Ready

[7:0]

ADC_VALUE

Detector ADC 8-Bit Output

0x0

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