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MCP48FVB01 数据表(PDF) 53 Page - Microchip Technology

部件名 MCP48FVB01
功能描述  8-/10-/12-Bit Single/Dual Voltage Output Volatile Digital-to-Analog Converters with SPI Interface
PDF  84 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP48FVB01 数据表(HTML) 53 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS20005466A-page 53
MCP48FVBXX
7.0.3
ERROR CONDITION
The Command Error (CMDERR) bit indicates if the
five address bits received (AD4:AD0) and the two
command
bits
received
(C1:C0)
are
a
valid
combination (see Figure 7-1). The CMDERR bit is
high if the combination is valid and low if the
combination is invalid.
SPI commands that do not have a multiple of eight
clocks are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
7.0.3.1
Aborting a Transmission
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks has
been received. If the CS pin is forced to the inactive
state (VIH), the serial interface is reset. Partial com-
mands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that noise corrupts
the value of the data being clocked into the
MCP48FVBXX or the SCK pin is injected with extra
clock pulses. This may cause data to be corrupted in
the device, or a Command Error to occur, since the
address and command bits were not a valid
combination. The extra SCK pulse will also cause the
SPI data (SDI) and clock (SCK) to be out of sync.
Forcing the CS pin to the inactive state (VIH) resets the
serial interface. The MCP48FVBXX’s SPI interface will
ignore activity on the SDI and SCK pins until the CS
pin transition to the active state is detected (VIH to VIL).
7.0.4
CONTINUOUS COMMANDS
The device supports the ability to execute commands
continuously. While the CS pin is in the active state
(VIL), any sequence of valid commands may be
received.
The following example is a valid sequence of events:
1.
CS pin driven active (VIL)
2.
Read
command
3.
Write
command (Volatile memory)
4.
CS pin driven inactive (VIH)
Note 1:
When data is not being received by the
MCP48FVBXX, it is recommended that the
CS pin be forced to the inactive level (VIH).
2:
It is also recommended that long
continuous command strings be broken
down into single commands or shorter
continuous
command
strings.
This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
commands.
Note 1:
It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is advisable to take the CS pin inactive
then force it back to the active state.
2:
It is also recommended that long
command strings should be broken down
into shorter command strings. This
reduces the probability of noise on the
SCK pin, corrupting the desired SPI
command string.



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