MCP48FVB01 datasheet(78/84 Pages) MICROCHIP

78 / 84 page

MCP48FVBXX

DS20005466A-page 78

 2015 Microchip Technology Inc.

B.7

Offset Error (EOS)

The offset error is the delta voltage of the VOUT voltage

from the ideal output voltage at the specified code.

This code is specified where the output amplifier is in

the linear operating range; for the MCP48FVBXX we

specify code 100 (decimal). Offset error does not

include gain error. Figure B-2 illustrates this.

This error is expressed in mV. Offset error can be neg-

ative or positive. The offset error can be calibrated by

software in application circuits.

FIGURE B-2:

OFFSET ERROR AND

ZERO-SCALE ERROR.

B.8

Offset Error Drift (EOSD)

Offset error drift is the variation in offset error due to a

change in ambient temperature. Offset error drift is

typically expressed in ppm/oC or µV/oC.

B.9

Gain Error (EG)

Gain error is a calculation based on the ideal slope

using the voltage boundaries for the linear range of the

output driver (ex code 100 and code 4000) (see

Figure B-3). The gain error calculation nullifies the

device’s offset error.

Gain error indicates how well the slope of the actual

transfer function matches the slope of the ideal transfer

function. Gain error is usually expressed as percent of

full-scale range (% of FSR) or in LSb. FSR is the ideal

full-scale voltage of the DAC (see Equation B-5).

FIGURE B-3:

GAIN ERROR AND

FULL-SCALE ERROR EXAMPLE.

EQUATION B-5:

EXAMPLE GAIN ERROR

B.10

Gain-Error Drift (EGD)

Gain-error drift is the variation in gain error due to a

change in ambient temperature. Gain error drift is

typically expressed in ppm/oC (of full-scale range).

Ideal Transfer

Actual

DAC Input Code

Zero-Scale

Error (EZS)

Offset

Function

100

4000

Error (EOS)

Transfer

Function

Ideal Transfer

Actual

DAC Input Code

Full-Scale

Error (EFS)

Gain Error (EG)

Function

100

4000

4095

VREF

Transfer

Function

(@ code = 4000)

Ideal Transfer

Function shifted by

Offset Error

(crosses at start of

defined linear range)

Where:

EG is expressed in % of full-scale range (FSR).

VOUT(@4000) = The measured DAC output

voltage at the specified code.

VOUT_Ideal(@4000) = The calculated DAC output

voltage at the specified code.

( 4000 * VLSb(Ideal) )

VOS = Measured offset voltage.

VFull Scale Range = Expected full-scale output

value (such as the VREF

voltage).

EG =

• 100

( VOUT(@4000) - VOS - VOUT_Ideal(@4000) )

VFull-Scale Range

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