–6–

REV. 0

ADP3161

the output voltage will droop and cause the PWRGD output to

signal that the output voltage has fallen out of its specified range.

Short Circuit Protection

The ADP3161 has multiple levels of short circuit protection to

ensure fail-safe operation. The sense resistor and the maximum

current sense threshold voltage given in the specifications set the

peak current limit.

When the load current exceeds the current limit, the excess

current discharges the output capacitor. When the output voltage is

output current is cut by reducing the current sense threshold

the oscillator frequency is reduced by a factor of five when

the output is 0 V. This further reduces the average current in

short circuit.

Power-Good Monitoring

The Power-Good comparator monitors the output voltage of the

supply via the FB pin. The PWRGD pin is an open drain output

whose high level (when connected to a pull-up resistor) indicates

that the output voltage is within the specified range of the nominal

output voltage requested by the VID DAC. PWRGD will go low if

the output is outside this range.

Output Crowbar

The ADP3161 includes a crowbar comparator that senses when

the output voltage rises higher than the specified trip thresh-

sets both PWM outputs low. The driver ICs turn off the high side

MOSFETs and turn on the low-side MOSFETs, thus pulling the

output down as the reversed current builds up in the inductors. If

the output overvoltage is due to a short of the high side MOSFET,

this action will current limit the input supply or blow its fuse,

protecting the microprocessor from destruction. The crowbar

comparator releases when the output drops below the specified

reset threshold, and the controller returns to normal operation if

the cause of the overvoltage failure does not persist.

Output Disable

The ADP3161 includes an output disable function that turns off

the control loop to bring the output voltage to 0 V. Because

an extra pin is not available, the disable feature is accomplished

by pulling the COMP pin to ground. When the COMP pin drops

below 0.56 V, the oscillator stops and both PWM signals are

driven low. This function does not place the part in a low quiescent

current shutdown state, and the reference voltage is still available.

The COMP pin should be pulled down with an open collector

or open drain type of output capable of sinking at least 2 mA.

APPLICATION INFORMATION

A VRM 8.4–Compliant Design Example

The design parameters for a typical high-performance Intel

Pentium III CPU application designed to meet Intel’s VRM 8.4

FMB specification (see Figure 1) are as follows:

(–80 mV) = 120 mV

() ( –)

VV

++

2

= 1.780 V

Output Current di/dt < 20 A/

µs.

1

2

3

4

8

7

6

5

BST

IN

DLY

VCC

DRVH

SW

PGND

DRVL

U2

ADP3412

U1

ADP3161

C14 TO C22

C20

D1

MBR052LTI

Q5

2N3904

Q3

IRL3803

Q4

IRL3803

C10

1 F

D2

MBR052LTI

C5

1 F

Z1

ZMM5236BCT

R5

2.4k

R8

330

C24

330pF

C25 1nF

C4

4.7 F

R6

10

C23

15nF

C26

4.7 F

C6

1 F

C9

1 F

R7

20

R4

4m

R1

1k

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

NC

VID3

VID2

VID1

VID0

COMP

FB

CT

VCC

REF

CS–

PWM1

PWM2

CS+

GND

1

2

3

4

8

7

6

5

BST

IN

DLY

VCC

DRVH

SW

PGND

DRVL

U3

ADP3412

1000 F

9

RUBYCON ZA SERIES

24m

ESR (EACH)

1.3V – 2.05V

26A

C7

15pF

C13

1000 F

16V

C12

1000 F

16V

C11

1000 F

16V

5V

15.1k

17.8k

C2

740pF

C1

150pF

L1

1 H

+

++

C8

15pF

L2

1 H

560

2.7nF

NC = NO CONNECT

Q1

IRL3803

Q2

IRL3803

• • •

PWRGD

Figure 1. 26 A Pentium III CPU Supply Circuit