–9–

REV. 0

ADP3161

mum gate drive voltage (the supply voltage to the ADP3412)

dictates whether standard threshold or logic-level threshold

ment for the power MOSFETs. When the ADP3161 is operating

in continuous mode, the simplifying assumption can be made

that in each phase one of the two MOSFETs is always conduct-

1.8 V, the duty ratio of the high-side MOSFET is:

D

V

V

HSF

OUT

IN

== 36%

(11)

The duty ratio of the low-side (synchronous rectifier) MOSFET is:

DD

LSF

HSF

==

164

–%

(12)

The maximum rms current of the high-side MOSFET during

normal operation is:

I

I

D

I

I

A

HSF MAX

O

HSF

L RIPPLE

O

()

()

.

=× +

×









=

2

1

3

79

2

2

(13)

The maximum rms current of the low-side MOSFET during

normal operation is:

II

D

D

A

LSF MAX

HSF MAX

LSF

HSF

()

()

.

== 10 5

(14)

dissipation. If 10% of the maximum output power is allowed for

MOSFET dissipation, the total dissipation in the four MOSFETs

of the two-phase converter will be:

PV

I

V

A

W

MOSFET TOTAL

OUT

O

()

..

.

.

=×

×

=

×

×

=

01

01 18

26

47

(15)

Allocating half of the total dissipation for the pair of high-side

MOSFETs and half for the pair of low-side MOSFETs, and

assuming that the resistive and switching losses of the high-side

MOSFET are equal, the required maximum MOSFET resis-

tances will be:

R

P

I

W

A

m

DS ON HS MAX

MOSFET TOTAL

HSF MAX

()

(

)

()

()

.

(.

)

.

=

×

=

×

=Ω

8

47

87 9

94

22

(16)

R

P

I

W

A

m

DS ON LS MAX

MOSFET TOTAL

LSF MAX

()

(

)

()

()

.

(.

)

.

=

×

=

×

=Ω

4

47

410 5

10 6

22

(17)

6 m

Ω nominal, 9 mΩ worst case) is a good choice for both the

high-side and low-side. The high-side MOSFET dissipation is:

PR

I

VI

Q

f

I

VQ

f

HSF

DS ON HS

HFS MAX

IN

L PK

G

SW

G

IN

RR

SW

=×

×

+×

×

()

()

(

)

()

2

2

(18)

where the second term represents the turn-off loss of the MOSFET

and the third term represents the turn-on loss due to the stored

charge in the body diode of the low-side MOSFET. (In the

the peak gate drive current provided by the ADP3412 is about

of the low-side MOSFET at the valley of the inductor current.

The data sheet of the IRL3803 gives 450 nC for the stored charge

at 71 A. That value corresponds to a stored charge of 80 nC

is the peak current in the inductor, or 15.85 A.)

Substituting the above data in Equation 18, and using the worst-

case value for the MOSFET resistance, yields a conduction loss

of 0.56 W, a turn-off loss of 1.1 W, and a turn-on loss of 0.08 W.

Thus the worst-case total loss in a high-side MOSFET is 1.74 W.

The worst-case low-side MOSFET dissipation is:

PR

I

m

A

W

LSF

DS ON LS

LSF MAX

=×

=

Ω ×

=

()

()

(.

)

22

910 5

1

(19)

(Note that there are no switching losses in the low-side MOSFET.)

In continuous inductor-current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

maximum output current. To prevent large voltage transients, a

low ESR input capacitor sized for the maximum rms current

must be used. The maximum rms capacitor current is given by:

I

I

DD

A

A

C RMS

O

HSF

HSF

()

()

.– (

.

)

.

=×

−

×

=

××

=

2

22

26

2

20 36

20 36

5 8

2

2

(20)

Note that the capacitor manufacturer’s ripple current ratings are

often based on only 2000 hours of life. This makes it advisable to

further derate the capacitor, or to choose a capacitor rated at a

higher temperature than required. Several capacitors may be

placed in parallel to meet size or height requirements in the

design. In this example, the input capacitor bank is formed by

three 1000

µF, 16 V Rubycon capacitors.

The ripple voltage across the three paralleled capacitors is:

V

I

n

ESR

n

D

nC

f

Am

FkHz

mV

C RIPPLE

OC

C

HSF

CIN

SW

()

.

=×

+

××









=

×

Ω +

××









=

26

2

24

3

036

3 1000

200

112

µ

(21)

To reduce the input-current di/dt to below the recommended

maximum of 0.1 A/

µs, an additional small inductor (L > 1 µH

@ 15 A) should be inserted between the converter and the sup-

ply bus. That inductor also acts as a filter between the converter

and the primary power source.

Feedback Loop Compensation Design for ADOPT

Optimized compensation of the ADP3161 allows the best pos-

sible containment of the peak-to-peak output voltage deviation.

Any practical switching power converter is inherently limited by

the inductor in its output current slew rate to a value much less

than the slew rate of the load. Therefore, any sudden change of

load current will initially flow through the output capacitors,

and assuming that the capacitance of the output capacitor is

larger than the critical value defined by Equation 5, this will

produce a peak output voltage deviation equal to the ESR of the

output capacitor times the load current change.