ADP3161JR datasheet(10/12 Pages) AD

10 / 12 page

–10–

REV. 0

ADP3161

The optimal implementation of voltage positioning, ADOPT,

will create an output impedance of the power converter that is

entirely resistive over the widest possible frequency range, includ-

ing dc, and equal to the maximum acceptable ESR of the output

capacitor array. With the resistive output impedance, the output

voltage will droop in proportion with the load current at any load

current slew rate; this ensures the optimal positioning and allows

the minimization of the output capacitor.

With an ideal current-mode-controlled converter, where the

average inductor current would respond without delay to the

command signal, the resistive output impedance could be achieved

by having a single-pole roll-off of the voltage gain of the voltage-

error amplifier. The pole frequency must coincide with the ESR

zero of the output capacitor. The ADP3161 uses constant frequency

current-mode control, which is known to have a nonideal, fre-

quency dependent command signal to inductor current transfer

function. The frequency dependence manifests in the form of a

pair of complex conjugate poles at one-half of the switching fre-

quency. A purely resistive output impedance could be achieved

by canceling the complex conjugate poles with zeros at the same

complex frequencies and adding a third pole equal to the ESR

zero of the output capacitor. Such a compensating network would

be quite complicated. Fortunately, in practice it is sufficient to

cancel the pair of complex conjugate poles with a single real zero

placed at one-half of the switching frequency. Although the end

result is not a perfectly resistive output impedance, the remaining

frequency dependence causes only a few percentage of deviation

from the ideal resistive response. The single-pole and single-

zero compensation can be easily implemented by terminating

the gm error amplifier with the parallel combination of a resistor

and a series RC network.

The first step in the design of the feedback loop compensation is

to determine the targeted output resistance, RE(MAX) of the power

converter using Equation 4. The compensation can then be

tailored to create that output impedance for the power converter,

and the quantity of output capacitors can be chosen to create a

net ESR that is less than or equal to RE(MAX).

The next step is to determine the total termination resistance of

the gm amplifier that will yield the correct output resistance:

mmho

SENSE

E MAX

××

×Ω

×Ω ×

=Ω

()

784

(22)

where nI is the division ratio from the output voltage signal of the

gm amplifier to the PWM comparator (CMP1), gm is the transcon-

ductance of the gm amplifier itself, and the factor of 2 is the result

of the two-phase configuration.

Once RT is known, the two resistors that make up the divider

from the REF pin to output of the gm amplifier (COMP pin)

must be calculated. The resistive divider introduces an offset to

the output of the gm amplifier that, when reflected back through

the gain of the gm stage, accurately positions the output voltage

near its allowed maximum at light load. Furthermore, the output

of the gm amplifier sets the current sense threshold voltage.

At no load, the current sense threshold is increased by the peak

of the ripple current in the inductor and reduced by the delay

between sensing when the current threshold has been reached

and when the high-side MOSFET actually turns off. These

two factors are combined with the inherent voltage at the output

of gm amplifier that commands a current sense threshold of

0 mV (VGNL0):

GNL

L RIPPLE

AVG

DCS

GNL

××

−

××

()

×Ω ×

−

××

Ω ×

51 78

1 25

()

(23)

The output voltage at no load (VONL) can be calculated by start-

ing with the VID setting, adding in the positive offset (V+),

subtracting half the ripple voltage, and then subtracting the

dominant error terms:

ONL

VID

WIN

VID

ONL

−

−×









−

Ω×

×+









∆

0007

002

83 5

1 824

–.

( .

)

(24)

With these two terms calculated, the divider resistors (RA for

the upper, and RB for the lower) can be calculated. Assuming

that the internal resistance of the gm amplifier (ROGM) is 200 k

Ω:

mmho

REF

GNL

ONL

VID

−−

−

Ω

−×

=Ω

–

()

.( .

– .

)

31 25

784

1824

17 6

(25)

Choosing the nearest 1% resistor value gives RB = 17.8 k

Ω.

Finally, RA is calculated:

OGM

−−

Ω

−

Ω

−

Ω

=Ω

784

200

17 8

15 1

(26)

Again, choosing the nearest 1% resistor value gives RA = 15.0 k

Ω.

The compensating capacitor can be calculated from the equation

kHz

OUT

OSC

−

××

×Ω

Ω

−

××

Ω

92 67

784

400

7 84

286

(27)

Choosing the nearest standard value yields 2.7 nF.

The resistance of the zero-setting resistor in series with the

compensating capacitor is

kHz

OSC

××

=Ω

2 7

400

590

ππ

(28)

The nearest 2.7 standard 5% resistor value is 560

Ω.

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