–12–

REV. 0

ADP3161

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead SOIC

(R-16A/SO-16)

16

9

8

1

0.1574 (4.00)

0.1497 (3.80)

0.3937 (10.00)

0.3859 (9.80)

0.050 (1.27)

BSC

PIN 1

0.2440 (6.20)

0.2284 (5.80)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

8

0

0.0196 (0.50)

0.0099 (0.25)

45

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

Signal Circuitry

15. The output voltage is sensed and regulated between the FB

pin and the GND pin (which connects to the signal ground

plane). The output current is sensed (as a voltage) by the

CS+ and CS– pins. In order to avoid differential mode noise

pickup in the sensed signal, the loop area should be small.

Thus the FB trace should be routed atop the signal ground

plane, and the CS+ and CS– pins should be routed as a

closely coupled pair (the CS+ pin should be over the signal

ground plane as well).

16. The CS+ and CS– traces should be Kelvin-connected to the

current sense resistor, so that the additional voltage drop due

to current flow on the PCB at the current sense resistor

connections, does not affect the sensed voltage.