MCP3564 datasheet(73/108 Pages) MICROCHIP

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DS20006181C-page 73

MCP3561/2/4

6.8.1

CONVERSION DATA READY

INTERRUPT

The data ready interrupt happens when a new

conversion is ready to be read on the ADCDATA register.

This event happens synchronously with DMCLK and at

each end of conversion. This interrupt is implemented

with three different and independent mechanisms:

STATUS byte on SDO, IRQ register Status bit, and IRQ

pin state.

STATUS byte on SDO. When the interrupt

occurs on the next STATUS byte transmitted on

SDO, the DR_STATUS bit will be logic low. Once

the STATUS byte has been transmitted, the

DR_STATUS bit appears as ‘1’ until a new

interrupt is present. If the interrupt occurs

between two STATUS byte transmissions, the

DR_STATUS bit on SDO will appear as equal to

‘0’ on the second reading.

IRQ register Status bit. When the interrupt

occurs, the DR_STATUS bit in the IRQ register

is set to ‘0’. Once the IRQ register has been fully

read, this DR_STATUS bit is reset to ‘1’. If the

interrupt occurs between two readings of the

IRQ register, the IRQ register Status bit appears

as equal to ‘0’ on the second reading.

IRQ pin state. The interrupt generates an IRQ

pin falling edge (transition to logic low) as soon

as it happens.

The data ready interrupt is cleared by the first of the

following two events:

• First falling edge of SCK during an ADC Output

Data register read

• 16 DMCLK clock periods before current

conversion ends

If the user does not read the ADCDATA register in time

in Continuous Conversion mode or in SCAN mode, the

IRQ pin will automatically reset to its Inactive state

16 DMCLKs prior to the new data ready interrupt. This

feature is designed in order to avoid the case where the

IRQ pin is logic low if the reading of ADC data is not

performed. The user can then determine exactly when

to expect the new data and can respect the tDODR

timing in all cases to ensure a proper reading of the

ADC data. See Figure 6-13 for more details.

FIGURE 6-13:

Data Ready Interrupt IRQ Pin Timing Diagram.

SPI

IRQ

TCON V

Transition time

tDOD R

Read A DC DATA1

1/DRCLK

TDRH

DATA1 can be read dur ing this time

Interrupt is cleared

at first SCK falling edge

after ADCDATA read start

ADCDATA

DATA1

DATA0

Interrupt is cleared

automatically if ADCDATA

has not been read in time

Read A DC DATA2

1/DRCLK

TDRH

DATA2 can be read dur ing this time

DATA2

Data Ready Interrupt

C OMM AN D By te

Read A DCDATA

C OMM AN D By te

Read A DCDATA

Transition time

tDOD R

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