ADPA1107

Data Sheet

Rev. 0 | Page 6 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

3

4

2

NIC

NIC

NIC

NIC

5

6

NIC

GND

7

RFIN

8

GND

9

NIC

21 NIC

22 NIC

11 12 13 14 15 16 17 18 19 20

31

ADPA1107

TOP VIEW

(Not to Scale)

23 VDET

24 GND

25 RFOUT

26 GND

27 VREF

28 NIC

29 NIC

30 NIC

10

NIC

32

33

34

35

36

37

38

39

40

NOTES

1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE

NOT CONNECTED INTERNALLY, HOWEVER, ALL DATA

SHOWN WAS MEASURED WITH THESE PINS CONNECTED

TO RF AND DC GROUND EXTERNALLY.

2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED

TO RF AND DC GROUND

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 to 4, 8 to 12, 14 to 17,

20 to 22, 28 to 31, 34 to 37, 40

NIC

Not Internally Connected. These pins are not connected internally, however, all data

shown was measured with the NIC pins connected to RF and dc ground externally.

5, 7, 24, 26

GND

The GND pins must be connected to RF and dc ground. See Figure 3 for the interface

schematic.

6

RFIN

RF Input. The RFIN pin is ac-coupled and matched to 50 Ω. See Figure 4 for the

interface schematic.

13, 38

VDD1B, VDD1A

Power Supply Voltage for the Amplifier. First stage drain bias. See Figure 4 for the

interface schematic.

18, 19, 32, 33

VDD2B, VDD2A

Power Supply Voltage for the Amplifier. Second stage drain bias. See Figure 5 for the

interface schematic.

23

VDET

Detector Diode to Measure RF Output Power. Output power detection via the VDET

pin requires the application of a dc bias voltage through an external series resistor.

temperature compensated dc voltage that is proportional to the RF output power.

See Figure 5 for the interface schematic.

25

RFOUT

RF Output. The RFOUT pin is ac-coupled and matched to 50 Ω. See Figure 5 for the

interface schematic.

27

VREF

Reference Diode for Temperature Compensation of VDET RF Output Power

Measurements. See Figure 6 for the interface schematic.

39

VGG1

Gate Control Voltage Pin. See Figure 4 and Figure 5 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to RF and dc ground.