Data Sheet

ADRF5515A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 15

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 4, 7, 9 to 11, 15, 16, 21, 23, 28, 30, 35,

36, 40

GND

Ground.

3

ANT-CHA

RF Input to Channel A.

5

SWCTRL‑CHAB

Control Voltage for Switches on Channel A and Channel B.

6

SWVDD‑CHAB

Supply Voltage for Switches on Channel A and Channel B.

8

ANT-CHB

RF Input to Channel B.

12

TERM-CHB

Termination Output. This pin is the transmitter path for Channel B.

13, 14, 18, 19, 25, 32, 33, 37, 38

NIC

Not Internally Connected. It is recommended to connect NIC to the RF ground of the PCB.

17

VDD1-CHB

Supply Voltage for Stage 1 LNA on Channel B.

20

VDD2-CHB

Supply Voltage for Stage 2 LNA on Channel B.

22

RXOUT-CHB

RF Output. This pin is the receiver path for Channel B. The RXOUT-CHB pin is ac-matched to 50 Ω. No

matching component is required. A dc blocking capacitor is required.

24

BP-CHB

Bypass Second Stage LNA of Channel B.

26

PD-CHAB

Power Down All Stages of LNA for Channel A and Channel B.

27

BP-CHA

Bypass Second Stage LNA of Channel A.

29

RXOUT-CHA

RF Output. This pin is the receiver path for Channel A. The RXOUT-CHA pin is ac matched to 50 Ω. No

matching component is required. A dc blocking capacitor is required.

31

VDD2-CHA

Supply Voltage for Stage 2 LNA on Channel A.

34

VDD1-CHA

Supply Voltage for Stage 1 LNA on Channel A.

39

TERM-CHA

Termination Output. This pin is the transmitter path for Channel A.

EPAD

Exposed Pad. The exposed pad must be connected to RF or dc ground.