PD70210AL datasheet(18/36 Pages) MICROCHIP

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Number

Designator

Description

HYST

This is the output of the UVLO comparator as shown in the Figure 1-2. “hysteresis

resistor” from HYST pin must be connected to VINS pin to create positive feedback

(and hysteresis). Initially, as the input voltage is rising, the VINS pin voltage is below

1.2V and so the output of the UVLO comparator is low, leading the hysteresis

resistor to fall in parallel to the lower resistor of the UVLO divider placed at the VINS

pin, assisting it to pull down the VINS pin voltage further. As soon as the rising

UVLO threshold is exceeded (VINS > 1.2V), the output of the UVLO comparator

suddenly goes high (up to VDD) and the hysteresis resistor, effectively comes

partially across the upper resistor of the UVLO divider, assisting it in to pull up the

voltage on the VINS pin. This feedback, therefore, increases the voltage on the

VINS pin. Now, the input rail has to fall to a much lower level to allow the VINS pin

voltage to fall below 1.2V. That is how hysteresis is created by positive feedback

action through the hysteresis resistor. The exact math is shown in the 5.

Applications Information section. Note that the HYST pin always toggles between

high or low depending on whether the voltage on the VINS pin is above or below

1.2V, respectively. This can always be used to indicate when the input rail is above

the programmed rising threshold and when it falls below the programmed falling

threshold.

SYNC

Synchronizes the LX7309 to a frequency higher than its default value as set on

RFREQ pin. The synchronizing clock must be 2x the desired sync frequency, with a

maximum synchronizing clock frequency of 1 MHz (for 500 kHz PWM frequency).

The PG pin’s rising edge occurs at the same instant as the rising edge of the clock

being applied on the SYNC pin.

RFREQ

Connect a programming resistor from this pin to IC ground (pin GND) to set the

switching frequency. A typical value of the programming resistor is 49.9k, and this

value provides a frequency of 215 kHz. Halving it roughly doubles the frequency,

whereas doubling it halves the frequency. Note that the converter is designed to

operate from 100 kHz to 500 kHz based on this pin.

Switching frequency equation:

where Freq is [Hz] and RFREQ is in [Ω]

For more information, see the 5.2 Setting Switching Frequency section.

This is the soft-start pin. Typically, a 0.1 µF capacitor, the “soft-start capacitor”, is

connected between this pin and IC ground (pin GND). The capacitor gets charged

up to 1.2V by an internal resistor, and the voltage on the capacitor, in effect, forms

the input voltage reference VREF of the error amplifier. But, note that this capacitor

serves other functions too; for example, it controls the rate of hiccupping under

overcurrent fault conditions. Therefore, even if the internal reference is not being

used (as in isolated topologies with a TL431 on the secondary side), the soft-start

capacitor is recommended to be in place always. The actual capacitor used is

determined by the application. For more information, see the 5.3 Setting Soft-Start

section.

RCLP

Low power clamp resistor. A resistor can be connected from this pin to IC ground

(pin GND) to set the exact level at which pulse-skipping mode is entered at light

loads. However, the usual default is to connect this pin directly to IC ground, in

which case pulse-skipping mode is disabled. The method to select the threshold

(and RCLP resistor value) is described in the 5. Applications Information section.

PD70211

Pin Configuration

Datasheet

DS00003672A-page 18

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