PD70210AL datasheet(17/36 Pages) MICROCHIP

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Number

Designator

Description

4P_AT_FLAG

Open drain output. The pin gets actively pulled low when a 4-pair version of a (non-

standard) Type 2 PD-PSE mutually identify each other via classification. There is a

minimum 80 ms delay from the moment when the input capacitor is fully charged to

this signal activity. Signal is referenced to VPN_OUT.

RREF

Bias current resistor. A 60.4k, 1% resistor is connected between RREF and IC

ground (VPN_IN).

RCLASS

Sets the Class of the PD. Connect RCLASS (programming resistor) between this

pin and IC ground (VPN_IN). Allowed values are 133Ω, 69.8Ω, 45.3Ω, and 30.9Ω

for Class 1, 2, 3, and 4 respectively. If RCLASS is not present, the PD draws up to 3

mA during classification, therefore, indicating Class 0 (default Type 1) to the PSE.

Signal is referenced to VPN_IN.

HD_FLAG

Open drain output. The pin gets actively pulled low when a 2-pair HDBaseT PD-

PSE mutually identify each other through classification. There is a minimum of 80

ms delay from the moment when the input capacitor is fully charged to this signal

activity. Signal is referenced to VPN_OUT.

AT_FLAG

Open drain output. This pin gets actively pulled low when a Type 2 PD-PSE

mutually identifies each other through classification. There is a minimum of 80 ms

delay from the moment when the input capacitor is fully charged to this signal

activity. Signal is referenced to VPN_OUT.

8, 9

VPN_IN

Lower rail of the incoming PSE voltage rail—from the negative terminal of the two

OR-ed bridge rectifiers (the corresponding upper PoE rail is VPP).

10, 11

VPN_OUT

This is in effect, the switched ground for establishing continuity to the PWM section

after successful detection, classification, and power-up. It is connected to the power

ground and PWM controller IC’s ground plane of the DC-DC converter section.

ENABLE

A logic-level input to enable the converter. It can be pulled up constantly, for

example, with a 100k resistor to VDD, to forcibly enable the converter, provided the

input supply has exceeded any applicable UVLO thresholds as set on the VINS pin

or on the VCC pin. Internally, the ENABLE pin goes to the input of an OR-gate, the

other input terminal of which is tied to “POK”—a signal provided by the front-end. If

the ENABLE pin is forced high, the output of the OR-gate goes high and the

converter is allowed to start (provided all UVLO’s are past). If the ENABLE pin is

held low, the internal node “POK” goes active/high when the PD’s front-end

conducts (power OK), so the OR-gate goes high once again. In this case, the

switching converter turns ON as required by the PoE standard. However, for

supporting wall adapters, injecting power after the front-end (at the input of the

converter), the converter can be turned ON forcefully, without the front-end signaling

“PGOOD”, by not tying the ENABLE pin low, but by tying it high (to VDD). That turns

ON the converter irrespective of the state of the front-end (conducting or not), and

whether there is any incoming PoE power or not.

VINS

The VINS pin is a programmable UVLO pin. The converter turns ON provided the

voltage on the VINS pin is above 1.2V (and VCC is not in UVLO, and ENABLE pin

is also high—connected to VDD, for example). The converter stops switching (turns

OFF) when the voltage on the VINS pin falls below 1.2V (or if ENABLE is taken low,

or if VCC falls outside its operating range). Thus, by connecting a voltage divider

between input rail and IC ground, the UVLO threshold to enable switching can be

set. However, to have a smooth startup, it is advisable to have some hysteresis too,

by means of a resistor between VINS and HYST as explained in pin-14.

PD70211

Pin Configuration

Datasheet

DS00003672A-page 17

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