PD70210AL datasheet(20/36 Pages) MICROCHIP

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Number

Designator

Description

Secondary gate driver. It drives a synchronous FET or an active clamp FET. It is

derived from VCC (~ 12 V), and has a 10Ω limiting resistor. Therefore, it can be

used to drive a gate-drive transformer directly. It is usually complementary to the

primary gate driver pin (PG). But, there is a typical 110 ns blanking time between

the two to prevent cross-conduction. SG is held firmly low in pulse-skip mode (if

allowed). It is also low during soft-start. It allows forced PWM (continuous

conduction) mode by allowing negative inductor currents. It does not support diode-

emulation mode (discontinuous conduction mode). However, in pulse-skip mode, as

the SG stays OFF, the converter automatically lapses into discontinuous conduction

mode through the body-diode of the synchronous FET. This pin can be left floating,

if unused.

PGND

Power ground (for internal SG and PG drivers). This is ideal for VCC decoupling

and the Primary-side current sense resistor’s lower terminal. GND and PGND can

be combined into a single large ground plane. Note that the power ground plane is

firmly connected to VPN_OUT, which is the drain side of the PD’s low-side pass-

FET (it stands for Negative Port Voltage Out).

CSN

The negative input of the internal current-sense voltage amplifier. Note that the

common-mode range of the differential current-sense amplifier is 2V and its gain is

5. This is used for high-side current sensing up to 2V. It is then placed on the

(steady) output side of a Buck inductor, and the maximum output voltage is 1.8V for

using this type of sensing. Ensure that CSN is at a lower voltage compared to the

positive input of the current-sense amplifier (CSP). Current sensing can also be

implemented in a more basic fashion for “low-side” sensing, with a resistor in the

return (ground) of the Buck. In that case, CSN is shown connected to IC ground.

However, to avoid noise from ground bounce, it is best to route this on the PCB in

Kelvin manner to the lower end of the sense resistor. This is important because the

peak operating voltage on the sense resistor is only 200 mV and PCB-related noise

can cause jitter in the switching waveform in current-mode control.

CSP

The positive input of the internal current-sense voltage amplifier. See description of

pin 28 (CSN). Note that the output of the current-sense amplifier is amplified five

times. Therefore, a 0.2V current-sense voltage translates to a 1V swing at the input

of the PWM comparator. Higher voltages lead to hiccup mode protection.

This stands for primary gate driver. It drives the main FET, and has a 5Ω or 10Ω

limiting drive resistor switched between a voltage close to VCC rail and the IC

ground. For guaranteeing proper shutdown during OFF time, it is necessary to add

a 470k resistor from PG to VINS, as shown in Figure 1.

Internal rail of –5V with respect to VCC, brought out only for decoupling purposes.

Connect a 0.1 µF ceramic cap very close, from this pin to VAUX_VCC pin.

VAUX_VCC

Auxiliary voltage rail from front-end to the VCC (supply) input of the PWM section.

The front-end provides a few mA of startup current for the PWM controller (at

typically 10.5V). Signal is referenced to VPN_OUT and is activated once front-end

power up sequence ends. After initial startup of PWM section, a bias winding can be

connected to this pin through a diode, to sustain the PWM section.

WA_EN

While this input is low (referenced to VPN_IN) the chip work according to internal

flow diagram. When this input is high, it enable wall adapter feature. Place 100 nF

to 1 uF/10V capacitor from WA_EN to VPN_IN pins, locate it close to device. When

WA_EN is no tused, connect it to VPN_IN. For further information, see the

Operation with an External DC Source section.

PD70211

Pin Configuration

Datasheet

DS00003672A-page 20

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