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PD70210AL 数据表(PDF) 21 Page - Microchip Technology |
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PD70210AL 数据表(HTML) 21 Page - Microchip Technology |
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21 / 36 page ![]() ...........continued Pin Number Designator Description 34 4P_HD_FLAG Open drain output. The pin gets actively pulled low when a 4-pair HDBaseT PD- PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT. 35 VPP Upper rail of the incoming PSE voltage rail—from the positive terminal of the two OR-ed bridge rectifiers (the corresponding lower PoE rail is VPN_IN). 36 RDET Internally connects to VPN_IN during detection phase and disengages after it is over. A 25 KΩ (or 24.9K), 1% resistor is connected between this pin and VPP. 37 EPAD Connected on PCB plane to VPN_IN. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 21 |
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