PLL650-01

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4

FUNCTIONAL DESCRIPTION

Selectable spread spectrum and output frequencies

The PLL650-01 provides selectable spread spectrum modulation and selectable output frequencies, as well as an

“output enable” selection input (pin 15). Selection is made by connecting specific pins to a logical “zero” or “one”,

according to the frequency selection tables shown on page 3.

In order to reduce the number of pins on the chip, the PLL650-01 uses pin 18 (REF/CS1) as a bi-directional pin

that serves as input (CS1) upon power-up, and as output (REF) as soon as the input has been latched.

Pins 1 (FS0), 5 (FS1), 19 (FS2), 20 (FS3), and 12 (FS4) are used as inputs to select the CLKA1, CLKA2, CLKB1,

CLKB2 output frequencies and spread spectrum (SST) modulations (as detailed in the frequency selection table on

page 3). Pins 11 (CS0) and 18 (REF/CS1) are used to select the CLKC1 and CLKC2 frequency outputs. As said

above, pin 18 is a bi-directional pin.

Pin 15 (OE) is the output enable selection input that tri-states (disables) all outputs when selected to “low” (logical

“zero”).

Connecting a selection pin to a logical “one”

In order to connect pins 1 (FS0), 5 (FS1), 19 (FS2), 20 (FS3), and 12 (FS4) to “high” (logical “one), the pins simply

need to be connected to VDD. Pins 15 and 18 have an internal pull-up resistor of 100k

Ω. This internal pull-up re-

sistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive load is connected be-

tween the pin and GND. For pins 15 and 18, no external pull-up resistor is therefore required for connecting a logi-

cal “one” upon. Note: since pin18 also is used as an output, it may happen that the output load present a low im-

pedance in comparison to the internal pull-up resistor. In this case, the internal pull-up resistor may not be suffi-

cient to pull the input up to a logical “one”, and an external pull-up resistor may be required.

Connecting a selection pin to a logical “zero”

Except for pin 18 (REF/CS1) that is bi-directional, all other input pins are input only. In order to connect them to a

logical “zero”, the pins simply need to be grounded. Connecting pin 18 to a logical “zero” will however require the

use of an external loading resistor between the pin and GND that has to be sufficiently small (compared to the in-

ternal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects

when the pin serves as output, the value of the external pull-down resistor should however be kept as large as

possible. In general, it is recommended to use an external resistor of around 10k

Ω (see Application Diagram).

Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this

resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down

resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough to achieve the

desired logical “zero”. This is particularly true when driving 74FXX TTL components.