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PLL650-01XC-R 数据表(PDF) 6 Page - PhaseLink Corporation |
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PLL650-01XC-R 数据表(HTML) 6 Page - PhaseLink Corporation |
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6 / 7 page ![]() PLL650-01 Low EMI Network LAN Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 6 2. AC Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Input Frequency 10 12.5 or 25 27 MHz Output Rise Time 0.8V to 2.0V with no load 1.5 ns Output Fall Time 2.0V to 0.8V with no load 1.5 ns Duty Cycle At VDD/2 45 50 60 % Max. Absolute Jitter Short term ±150 ps Max. Jitter, cycle to cycle 80 ps 3. DC Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Operating Voltage VDD 2.97 3.63 V Input High Voltage VIH VDD /2 V Input Low Voltage VIL VDD /2 VDD /2 - 1 V Input High Voltage VIH For all Tri-level input VDD -0.5 V Input Low Voltage VIL For all Tri-level input 0.5 V Input High Voltage VIH For all normal input 2 V Input Low Voltage VIL For all normal input 0.8 V Output High Voltage VOH IOH = -25mA 2.4 V Output Low Voltage VOL IOL = 25mA 0.4 V Output High Voltage At CMOS Level VOH IOH = -8mA VDD -0.4 V Operating Supply Current IDD No Load 35 mA Short-circuit Current IS ±50 mA Internal pull-up resistor Rup OE, CS1 100 k Ω |
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