PLL650-01

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Full CMOS output swing with 25 mA output drive

capability at TTL levels.

• Advanced, low power, sub-micron CMOS

process.

• 25.0MHz fundamental crystal or reference clock

signal.

• Six output clocks with selectable frequencies.

• SDRAM frequencies of 67,83,100, and 133MHz.

• Spread Spectrum Technology selectable for EMI

Reduction from

±0.25% to ±0.5% center.

• Buffered crystal reference output.

• Ideal for Network switches.

• 3.3V operation.

• Available in 150mil 20-Pin SSOP.

DESCRIPTION

The PLL650-01 is a low cost, low jitter, high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques,

the chip accepts 25.0MHz from a crystal or a refer-

ence clock, and produces multiple outputs clocks for

network chips, PCI devices, SDRAM, and ASICs.

PIN CONFIGURATION

Note: ^: 100k

Ω internal pull-up. *: Bi-directional pin. The value of

CS1 is latched upon power-up. When no external pull-down re-

sistor is connected to the pin, the internal pull-up results in a

default high value for CS1. An external 10k

Ω pull-down resis-

tor is recommended to set CS1 to low.

BLOCK DIAGRAM

XTAL

OSC

CLKA1

REFOUT

OE

XIN

XOUT

CLKA2

CLKB1

CLKB2

CLKC1

CLKC2

Control

Logic

FS (0:4)

CS (0:1)

1

2

3

4

5

6

7

8

9

10

14

15

16

17

18

19

20

13

12

11

FS0

XOUT

XIN

VDD

FS1

GND

CLKC1

CLKC2

CLKB2

CLKB1

FS3

FS2

REF/CS1*^

CLKA1

VDD

OE^

GND

CLKA2

FS4

CS0