MPC7441 datasheet(39/56 Pages) NXP

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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

Figure 18. Driver Impedance Measurement

Table 15 summarizes the signal impedance results. The impedance increases with junction temperature

and is relatively unaffected by bus voltage.

9.6

Pull-Up/Pull-Down Resistor Requirements

The MPC7447A requires high-resistive (weak: 4.7 K

Ω) pull-up resistors on several control pins of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the MPC7447A or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being factory test pins must be pulled up to OVDD or down to GND to ensure

proper device operation. The pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:3]; the

pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. The CKSTP_IN signal should

likewise be pulled up through a pull-up resistor (weak or stronger: 4.7 K

Ω–1 KΩ) to prevent erroneous

assertions of this signal.

In addition, the MPC7447A has one open-drain style output that requires a pull-up resistor (weak or

stronger: 4.7 K

Ω–1 KΩ) if it is used by the system. This pin is CKSTP_OUT.

If pull-down resistors are used to configure BVSEL, the resistors should be less than 250

Ω (see Table 12).

Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down

resistors (1 K

Ω or less) are recommended to configure these signals in order to protect against erroneous

switching due to ground bounce, power supply noise or noise coupling.

Table 15. Impedance Characteristics

VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C

Impedance

Processor Bus

Unit

Typical

33–42

Maximum

31–51

OVDD

OGND

Pad

Data

SW1

SW2

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