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IMX7ULPCECB2 数据表(PDF) 72 Page - NXP Semiconductors |
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IMX7ULPCECB2 数据表(HTML) 72 Page - NXP Semiconductors |
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72 / 122 page  SDA HD; STA tHD; DAT tLOW tSU; DAT tHIGH tSU; STA SR P S S tHD; STA tSP tSU; STO tBUF tf tr tf tr SCL t Figure 19. Timing definition for standard, fast, and fast plus devices on the I2C bus Table 38. I 2C timing (High speed mode) Parameter Symbol Minimum Maximum Unit SCLH Clock Frequency fSCLH 0 3.4 MHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 160 — ns LOW period of the SCLH clock tLOW 160 — ns HIGH period of the SCLH clock tHIGH 60 — ns Set-up time for a repeated START condition tSU; STA 160 — ns Data hold time for I2C bus devices tHD; DAT 0 70 ns Data set-up time tSU; DAT 10 — ns Rise time of SCLH signal trCL 10 40 ns Rise time of SCLH signal after a repeated START condition and after an acknowledge bit trCL1 10 80 ns Fall time of SCLH signal tfCL 10 40 ns Rise time of SDAH signal trDA 10 80 ns Fall time of SDAH signal tfDA 10 80 ns Set-up time for STOP condition tSU; STO 160 — ns Pulse width of spikes that must be suppressed by the input filter tSP 0 10 ns 8.1.6.3 Low Power Serial Peripheral Interface (LPSPI) switching specifications—application domain The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. See the LPSPI chapter of the chip reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. Specifications—application domain 72 i.MX 7ULP Applications Processor—Consumer, Rev. 0, 09/2020 NXP Semiconductors |
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