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IMX7ULPCECB2 数据表(PDF) 80 Page - NXP Semiconductors |
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IMX7ULPCECB2 数据表(HTML) 80 Page - NXP Semiconductors |
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80 / 122 page  9.1 Power sequencing—real-time domain See Power sequencing—system. 9.2 Peripheral operating requirements and behaviors—real-time domain 9.2.1 QuadSPI AC specifications • All data is based on a negative edge data launch from the device and a positive edge data capture, as shown in the timing diagrams in this section. • Measurements are with a load of 10 pF on output pins. Input slew: 2 ns • Timings assume a setting of 0x0004_000x for QuadSPI _SMPR register (see the reference manual for details). SDR mode 1 2 3 Tck Tcss Tcsh Tis Tih Clock SFCK CS Data in Figure 27. QuadSPI input timing (SDR mode) diagram NOTE • The timing values below are with default settings for sampling registers like QuadSPI_SMPR. • A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. • Frequency calculator guidelines (Max read frequency) for any frequency: SCR > (Flash access time)max + (Tis)max Specifications—real-time domain 80 i.MX 7ULP Applications Processor—Consumer, Rev. 0, 09/2020 NXP Semiconductors |
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