VC-830

DS20006510B-page 8

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2021 Microchip Technology Inc.

3.2

LVDS Application Diagrams

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused

output should not be left unterminated because if one of the two outputs is left open, it will result in excessive jitter on

both. PCB layout must take this and 50Ω impedance matching into account. Load matching and power supply noise are

the main contributors to jitter related problems.

FIGURE 3-3:

LVDS-to-LVDS Connection,

Internal 100Ω Resistor.

Some LVDS structures have an internal 100Ω resistor

on the input and do not need additional components.

AC blocking capacitors can be used if the DC levels are

incompatible.

FIGURE 3-4:

LVDS-to-LVDS Connection.

Some input structures may not have an internal 100Ω

resistor on the input and will need an external 100Ω

resistor located at the receiver for impedance

matching. Figure 3-4 is optimized to reduce common

mode noise. Additionally, the input may have an

internal DC bias that may not be compatible with LVDS

levels. AC blocking capacitors, such as 0.1 µF, should

be used in this case.