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amplitude and a rotation of the signal phase. To compensate for these effects, the FFT is followed by a

Frequency domain equaliser (FEQ) and a Rotor (phase shifter).

In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the mapper

into a time domain representation. The IFFT block is preceded by a Fine Tune Gain and a Rotor stage,

allowing for a compensation of the possible frequency mismatch between the master clock frequency and

the transmitter clock frequency (which may be locked to another reference).

The FFT module is a slave DSP engine controlled by the transceiver controller. It works off line and com-

municates with the other blocks via buffers controlled by the DSTU (DMT Symbol Timing Unit)block. The

DSP executes a program stored in a RAM area, a very flexible implementation open for future enhance-

ments.

Figure 5. DMT Modem

DPLL

The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock fre-

quencies at the transmitter and receiver do not match exactly. The phase error is filtered and integrated

by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate

to deal with the frequency mismatch. In particular, small accumulated phase errors can be compensated

in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are com-

pensated in the time domain by inserting or deleting clock cycles in the sample input sequence.

Mapper/Demapper, Monitor, Trellis Coding, FEQ Update

The Demapper converts the constellation points computed by the FFT to a block of bits. This essentially

consists in identifying a point in a 2D QAM constellation plane. The Demapper supports trellis coded de-

modulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the Demapper

receives an indication for the most likely constellation subset to be used. In the transmit direction, the Map-

per performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy

representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to im-

prove the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme.

The Monitor computes error parameters for carriers specified in the Demapper process. Those parame-

ters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc.

A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures

generation, loss of frame, etc.

Demapper

Rotor

FEQ

FEQ

Coefficients

FEQ

Update

FFT

From

DSP PE

Monitor

Monitor Indications

Trellis

coding