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MTC20455

Table 13. Transmitted bits assigned to signal/time slot for muxed-line interface

Table 14. MCLK, AC Electrical Characteristics

Table 15. AFTXD AC Electrical Characteristics

Table 16. CTRLDATA AC Electrical Characteristics

Figure 10. Analog front end receive interface timing diagram

Cycles

01

23

45

67

line 0

line 1

line 2

line 3

AFTXD_1[0]

b0

b8

b0

b8

b0

b8

b0

b8

AFTXD_1[1]

b1

b9

b1

b9

b1

b9

b1

b9

AFTXD_1[2]

b2

b10

b2

b10

b2

b10

b2

b10

AFTXD_1[3]

b3

b11

b3

b11

b3

b11

b3

b11

AFTXD_2[0]

b4

b12

b4

b12

b4

b12

b4

b12

AFTXD_2[1]

b5

b13

b5

b13

b5

b13

b5

b13

AFTXD_2[2]

b6

b14

b6

b14

b6

b14

b6

b14

AFTXD_2[3]

b7

b15

b7

b15

b7

b15

b7

b15

AC Electrical Characteristics for MCLK_i

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

F

Clock Frequency

35.328

MHz

Tper

Clock Period

28.3

ns

Th

Clock duty cycle

40

60

%

AC Electrical Characteristics for AFTXD_i

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Tva

Data valid time

20 pF load

16

ns

Tha

Data hold time

20 pF load

4

ns

AC Electrical Characteristics for CTRLDATA_i

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Tvb

Data valid time

20 pF load

20

ns

Thb

Data hold time

20 pF load

4

ns

MCLK_i

Ts

AFRXD_i

Th

CLWD_i