MTC20455

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Table 17. AFRXD AC Electrical Characteristics

Digital Interface

With a Utopia Level 2 Interface the ATM forum takes the ATM layer chip as a reference. It defines the

direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM

direction is referred to as the receive direction. Fig.9 shows the interconnection between ATM and PHY

layer devices. Tx reference and Rx reference are supported for network timing.

The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock

cycles. Both transmit and receive interfaces are synchronised on clocks generated by the ATM layer chip,

and as no specific relationship between Receive and Transmit clock is assumed, they must be regarded

as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints

of the physical layer and the ATM layer.

The UTOPIA level 2 supports point to multi-point configurations by introducing an addressing capability

and by making a distinction between polling and selecting a device:

– the ATM chip polls a specific physical layer chip by putting its address on the address bus when the

enable (notTxEnb/notRxEnb) line is asserted. The addressed physical layer answers the next cycle

via a cell available line (TxClav/RxClav) reflecting its status at that time.

– the ATM chip selects a specific physical layer chip by putting its address on the address bus when

the enable line is deasserted and asserting the enable line on the next cycle. The addressed physical

layer chip will be the target or source of the next cell transfer.

Figure 11. Signals at Utopia Level 2 Interface

AC Electrical Characteristics for AFRXD

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Ts

Data setup time

5

ns

Th

Data setup time

1

ns

PHY

Receive

ATM

Receive

RxAddr

5

notRxEnb

RxClk

RxClav

1

RxData

8

RxSOC

TxAddr

5

TxData

8

notTxEnb

TxSOC

TxClk

TxClav

1

PHY

Transmit

ATM

Transmit

PHY

ATM