SAMA5D2 datasheet(4/56 Pages) MICROCHIP

4 / 56 page

Features

• Arm Cortex-A5 Core

– ARMv7-A architecture

– Arm TrustZone®

– NEON

™ Media Processing Engine

– Up to 500 MHz

– ETM/ETB 8 Kbytes

• Memory Architecture

– Memory Management Unit

– 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache

– 128-Kbyte L2 cache configurable to be used as an internal SRAM

– DDR2-SDRAM memory up to 1 Gb

– LPDDR2-SDRAM memory up to 2 Gb

– One 128-Kbyte scrambled internal SRAM

– One 160-Kbyte internal ROM

• 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader

• 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table

– High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting

Winbond DDR2-SDRAM up to 1 Gb, including “on-the-fly” encryption/decryption path

– High-bandwidth scramblable 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting

AP memory LPDDR2-SDRAM up to 2 Gb , including “on-the-fly” encryption/ decryption path

– 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)

• System Running up to 166 MHz

– Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-

Time Clock (RTC) with clock calibration

– One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed

– Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)

– Internal low-power 12 MHz RC and 32 KHz typical RC

– Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator

– 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers

– 64-bit Advanced Interrupt Controller (AIC)

– 64-bit Secure Advanced Interrupt Controller (SAIC)

– Three programmable external clock signals

• Low-Power Modes

– Ultra-Low-Power mode with fast wake-up capability

– Low-Power Backup mode with 5-Kbyte SRAM and SleepWalking™ features

• Wake-up from up to nine wake-up pins, UART reception, analog comparison

• Fast wake-up capability

• Extended Backup mode with LPDDR2/DDR2-SDRAM in Self-Refresh mode

• Peripherals

– LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit

parallel RGB

– ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel

12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface

– Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D

amplifier

– One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)

– One Pulse Density Modulation Interface Controller (PDMIC)

SAMA5D2 SIP

Features

Datasheet

DS60001484D-page 4

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