ADP5092ACPZ-1-R7 datasheet(24/28 Pages) AD

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ADP5091/ADP5092

Data Sheet

Rev. A | Page 24 of 28

CAPACITOR SELECTION

Low leakage capacitors are required for ultralow power

applications that are sensitive to the leakage current. Any

leakage from the capacitors reduces efficiency, increases the

quiescent current, and degrades the MPPT effectiveness.

Input Capacitor

A capacitor (CIN) connected to the VIN pin and the PGND pin

stores energy from the input source. For the energy harvester,

capacitive behavior dominates the source impedance. Scale the

input capacitor according to the value of the output capacitance

of the energy harvester; a minimum of 10 µF is recommended.

For the primary battery application, a larger capacitance helps

to reduce the input voltage ripple and keeps the source current

stable to extend the battery life.

SYS Capacitor

The ADP5091/ADP5092 require two capacitors to be connected

between the SYS pin and the PGND pin. Connect a low ESR

ceramic capacitor of at least 4.7 µF parallel to a high frequency,

0.1 µF bypass capacitor. Connect the bypass capacitor as close as

possible between SYS and PGND.

REG_OUT Capacitor

The ADP5091/ADP5092 regulated output is designed for

operation with small, space-saving ceramic capacitors but

functions with the most commonly used capacitors as long as

care is taken with regard to the effective series resistance (ESR)

value. The ESR of the output capacitor affects stability of the

LDO control loop. A minimum capacitance of 4.7 µF with an

ESR of 1 Ω or less is recommended to ensure stability of the

regulated output. Transient response to changes in load current

is also affected by output capacitance. Using a larger value of

output capacitance improves the transient response of the

regulated output to large changes in load current.

CBP Capacitor

The operation of the MPPT pin depends on the sampled value

of the OCV. The voltage stored on the CBP capacitor regulates

to the VIN pin. This capacitor is sensitive to leakage because the

holding period is around 16 sec. As the capacitor voltage drops

due to leakage, the VIN regulation voltage also drops and

influences the effectiveness of MPPT. When the IC junction

temperature exceeds 85°C, a larger capacitance is beneficial to

the effectiveness of MPPT, and for a higher CPB pin leakage

current. It is recommended to keep the same RC time constant

of the MPPT resistors and CBP capacitor (up to 22 µF) as shown

in the typical application circuit in Figure 45. Considering the

time constant of the MPPT resistor divide and the CBP capacitor, a

low leakage X7R or C0G 10 nF ceramic capacitor is recommended.

LAYOUT AND ASSEMBLY CONSIDERATIONS

Carefully consider the printed circuit board (PCB) layout

during the design of the switching power supply, especially at

high peak currents and high switching frequency. Therefore, it

is recommended to use wide and short traces for the main power

path and the power ground paths. Place the input capacitors,

output capacitors, inductor, and storage elements as close as

possible to the IC. It is most important for the boost regulator to

minimize the power path from output to ground. Therefore,

place the output capacitor as close as possible between the SYS

pin and the PGND pin. Keep a minimum power path from the

input capacitor to the inductor from the VIN pin to the PGND

pin. Place the input capacitor as close as possible between the

VIN pin and the PGND pin, and place the inductor close to the

VIN pin and the SW pin. It is best to use vias and bottom traces

for connecting the inductors to their respective pins. To minimize

noise pickup by the high impedance threshold setting nodes

(REF, TERM, SETBK, SETSD, and SETPG), place the external

resistors close to the IC with short traces.

The CBP capacitor must hold the MPPT voltage for 16 sec,

because any leakage can degrade the MPPT effectiveness. During

board assembly and cleaning, contaminants such as solder flux

and residue may form parasitic resistance to ground, especially

in humid environments with fast airflow. Contamination can

significantly degrade the voltage regulation and change threshold

levels set by the external resistors. Therefore, it is recommended

that no ground planes be poured near the CBP capacitor or the

threshold setting resistors. In addition, carefully clean the boards. If

possible, clean ionic contamination with deionized water for the

CBP capacitor and the threshold setting resistors.

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