ADP5092ACPZ-1-R7 datasheet(18/28 Pages) AD

18 / 28 page

ADP5091/ADP5092

Data Sheet

Rev. A | Page 18 of 28

REG_GOOD (ADP5092 ONLY)

A logic high on the REG_GOOD pin indicates that the REG_OUT

voltage is above 92.5% (typical) of its nominal output for a delay

time greater than approximately 2 ms. The logic high level on

REG_GOOD is equal to the REG_OUT voltage, and the logic low

level is ground. When the REG_OUT voltage falls below a 2%

hysteresis (typical) of the rising threshold, the REG_GOOD pin

goes low. The logic high level has about 11.6 kΩ internally in

series to limit the available current.

ENERGY STORAGE CHARGE MANAGEMENT

Energy storage is connected to the BAT pin. The storage can be

a rechargeable battery, super capacitor, or 100 µF or larger

capacitor. The energy storage controller manages the charging

and discharging operations, monitors the SYS pin voltage, and

asserts the PGOOD signal high when it is above the threshold

programmed at the SETPG pin.

When the BAT pin voltage exceeds the battery terminal charging

threshold programmed at the TERM pin, the boost operation

terminates to prevent battery overcharging. The battery terminal

charging threshold is programmable from 2.2 V to 5.2 V. When

the BAT voltage drops below the battery stop charging threshold

level programmed at the SETSD pin, the switches between the

BAT pin and the SYS pin are turned off to prevent a deep, destruc-

tive battery discharge, and the boost operates in asynchronous

mode. Although there is no current limit at the SYS and the

BAT pins, it is recommended to limit the system load current

to lower than 1000 mA. The large system load current generates a

droop between the SYS pin and the rechargeable battery at the

BAT pin, with consideration given to the resistance of the SYS

switch, the BAT switch, and the rechargeable battery internal

resistance.

When no input source is attached, discharge the SYS pin to

ground before attaching a storage element to the BAT pin.

After hot plugging a charged storage element, release the SYS pin

because a SYS voltage that is less than the end of the cold start

operation threshold (VSYS_TH) results in the BAT switch remaining

off to protect the storage element until the SYS voltage reaches

VSYS_TH. The BAT switches remaining off can also be described

as store mode, a state with the lowest leakage (3.5 nA typical)

that allows a long store period without discharging the storage

element on BAT.

BACKUP STORAGE PATH

The ADP5091/ADP5092 provide an optional backup storage

energy path, an integrated backup controller, and two back to

back power switches between the BACK_UP pin and the SYS

pin. When the system operates at a condition where the harvested

and stored energy is periodically insufficient, attach a backup

energy storage element to the BACK_UP pin.

The backup controller enables when the SYS voltage exceeds the

end of the cold start operation threshold (VSYS_TH). Before the BAT

voltage lowers the SETBK threshold, the backup switches turn

off. While the BAT voltage is less than the SETBK threshold, the

switches status depends on the voltage level of the BACK_UP pin

and the BAT pin. The internal BACK_UP_Mx and BACK_UP

control circuit automatically determine the BACK_UP switches

(BACK_UP_M1 and BACK_UP_M2) on/off status and selects

the high voltage terminal as the power source of SYS. The 190 mV

(typical) comparator input offset of the BAT pin prevents the

input source and the BAT pin from charging the BACK_UP pin

(see Figure 44).

In addition, the backup storage element can bypass the cold

startup with inrush current protection circuitry. Nevertheless,

the current capability is only 250 µA (typical) when plugging in

the backup battery before completing the cold start. It is recom-

mended to restrict the system load current from the SYS pin to

ensure that the power path can enter normal operation status.

Table 9 explains the power path working state. For long-term

store mode, disconnect the backup storage element and then

discharge SYS to ground.

ADP5092ACPZ-1-R7 数据表(PDF) 18 Page - Analog Devices

ADP5092ACPZ-1-R7 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载