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ADUCM4050BCPZ-R7 数据表(PDF) 13 Page - Analog Devices |
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ADUCM4050BCPZ-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 46 page  Data Sheet ADuCM4050 Rev. A | Page 13 of 46 TIMING SPECIFICATIONS Reset Timing Table 13. Parameter Symbol Min Typ Max Unit RESET TIMING REQUIREMENTS SYS_HWRST Asserted Pulse Width Low1 tWRST 4 µs 1 Applies after power-up sequence is complete. SYS_HWRST tWRST Figure 2. Reset Timing Serial Ports Timing Table 14. Parameter Symbol Min Typ Max Unit Test Conditions/Comments EXTERNAL CLOCK SERIAL PORTS Timing Requirements Frame Sync Setup Before SPORT Clock1 tSFSE 5 ns Externally generated frame sync in transmit or receive mode Frame Sync Hold After SPORT Clock1 tHFSE 5 ns Externally generated frame sync in transmit or receive mode Receive Data Setup Before Receive SPORT Clock1 tSDRE 5 ns Receive Data Hold After SPORT Clock1 tHDRE 8 ns SPORT Clock Width2 tSCLKW 38.5 ns SPORT Clock Period2 tSPTCLK 77 ns Switching Characteristics3 Frame Sync Delay After SPORT Clock tDFSE 20 ns Internally generated frame sync in transmit or receive mode Frame Sync Hold After SPORT Clock tHOFSE 2 ns Internally generated frame sync in transmit or receive mode Transmit Data Delay After Transmit SPORT Clock tDDTE 20 ns Transmit Data Hold After Transmit SPORT Clock tHDTE 1 ns INTERNAL CLOCK SERIAL PORTS Timing Requirements1 Receive Data Setup Before SPORT Clock tSDRI 25 ns Receive Data Hold After SPORT Clock tHDRI 0 ns Switching Characteristics Frame Sync Delay After SPORT Clock3 tDFSI 20 ns Internally generated frame sync in transmit or receive mode Frame Sync Hold After SPORT Clock3 tHOFSI −8 ns Internally generated frame sync in transmit or receive mode Transmit Data Delay After SPORT Clock3 tDDTI 20 ns Transmit Data Hold After SPORT Clock3 tHDTI −7 ns SPORT Clock Width tSCLKIW tPCLK − 1.5 ns SPORT Clock Period tSPTCLK (2 × tPLCK) − 1 ns |
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