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ADUCM4050BCPZ-R7 数据表(PDF) 16 Page - Analog Devices |
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ADUCM4050BCPZ-R7 数据表(HTML) 16 Page - Analog Devices |
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16 / 46 page  ADuCM4050 Data Sheet Rev. A | Page 16 of 46 SPI Timing Table 15. Parameter1 Symbol Min Typ Max Unit SPI MASTER MODE TIMING Timing Requirements Chip Select (CS) to Serial Clock (SCLK) Edge tCS (2 × tPCLK) − 6.5 ns SCLK Low Pulse Width tSL tPCLK − 3.5 ns SCLK High Pulse Width tSH tPCLK − 3.5 ns Data Input Setup Time Before SCLK Edge tDSU 5 ns Data Input Hold Time After SCLK Edge tDHD 20 ns Switching Characteristics Data Output Valid After SCLK Edge tDAV 25 ns Data Output Setup Before SCLK Edge tDOSU tPCLK − 2.2 ns CS High After SCLK Edge tSFS tPCLK + 2 ns High Speed SPI (SPIH) MASTER MODE TIMING Timing Requirements CS to SCLK Edge tCS (2 × tPCLK) − 6.5 ns SCLK Low Pulse Width tSL tPCLK − 2 ns SCLK High Pulse Width tSH tPCLK − 2 ns Data Input Setup Time Before SCLK Edge tDSU 3.5 ns Data Input Hold Time After SCLK Edge tDHD 12 ns Switching Characteristics Data Output Valid After SCLK Edge tDAV 12.5 ns Data Output Setup Before SCLK Edge tDOSU tPCLK − 2.2 ns CS High After SCLK Edge tSFS tPCLK + 2 ns SPI SLAVE MODE TIMING Timing Requirements CS to SCLK Edge tCS 38.5 ns SCLK Low Pulse Width tSL 38.5 ns SCLK High Pulse Width tSH 38.5 ns Data Input Setup Time Before SCLK Edge tDSU 6 ns Data Input Hold Time After SCLK Edge tDHD 8 ns Switching Characteristics Data Output Valid After SCLK Edge tDAV 20 ns Data Output Valid After CS Edge tDOCS 20 ns CS High After SCLK Edge tSFS 38.5 ns SPIH SLAVE MODE TIMING Timing Requirements CS to SCLK Edge tCS 19.23 ns SCLK Low Pulse Width tSL 19.23 ns SCLK High Pulse Width tSH 19.23 ns Data Input Setup Time Before SCLK Edge tDSU 1 Data Input Hold Time After SCLK Edge tDHD 1 Switching Characteristics Data Output Valid After SCLK Edge tDAV 15 ns Data Output Valid After CS Edge tDOCS 15 ns CS High After SCLK Edge tSFS 19.23 ns 1 These specifications are characterized with respect to double drive strength. |
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