Data Sheet

ADP5302

Rev. B | Page 7 of 22

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EN 1

STOP 2

SYNC/MODE 3

VID 4

FB 5

10 PVIN

PIN 1

INDICATOR

NOTES

1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LARGE

EXTERNAL COPPER GROUND PLANE UNDERNEATH THE

IC FOR THERMAL DISSIPATION.

9 SW

8 PGND

7 AGND

6 VINOK

ADP5302

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN

Enable Input for the Regulator. A logic low on this pin disables the regulator.

2

STOP

Stop Switching Input Signal. When this pin is logic high, the regulator stops switching. When this pin is logic

low, the regulator resumes switching.

3

SYNC/MODE

Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock,

connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz.

PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM

mode. When this pin is logic low, the regulator operates in hysteresis mode.

4

VID

voltage of the regulator (see Table 5).

5

FB

Feedback Sensing Input for the Regulator.

6

VINOK

Input Power-Good Signal. This open-drain output is the power-good signal for the input voltage.

7

AGND

Analog Ground.

8

PGND

Power Ground.

9

SW

Switching Node Output for the Regulator.

10

PVIN

Power Input for the Regulator.

EPAD

EPAD

Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for

thermal dissipation.