Data Sheet

ADP5302

Rev. B | Page 15 of 22

All individual VID settings are available as internally fixed options.

Contact your local Analog Devices, Inc., sales or distribution

representative for more information on generating new models.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO circuitry monitors the input voltage level on the

PVIN pin. If the input voltage falls below 2.00 V (typical), the

regulator turns off. After the input voltage rises above 2.06 V

(typical), the soft start period initiates, and the regulator is

enabled when the EN pin is high.

ENABLE/DISABLE

The ADP5302 includes a separate enable pin. A logic high in the

enable pin starts the regulator. Due to the low quiescent current

design, it is typical for the regulator to start switching after a delay

of few milliseconds from the enable pin (EN) being pulled high.

A logic low on the enable pin immediately disables the regulator

and brings the regulator into an extremely low current consump-

tion state.

CURRENT LIMIT

The buck regulators in the ADP5302 have protection circuitry

that limits the direction and the amount of current to a certain

level that flows through the high-side MOSFET and the low-

side MOSFET in cycle by cycle mode. The positive current limit

on the high-side MOSFET limits the amount of current that can

flow from the input to the output. The negative current limit on

the low-side MOSFET prevents the inductor current from

reversing direction and flowing out of the load.

SHORT-CIRCUIT PROTECTION

The buck regulators in ADP5302 includes frequency foldback to

prevent current runaway on a hard short. When the output voltage

at the feedback pin falls below 0.3 V (typical), indicating the

possibility of a hard short at the output, the switching frequency

in PWM mode is reduced to one-fourth of the internal oscillator

frequency. The reduction in the switching frequency allows more

time for the inductor to discharge, preventing a runaway of

output current.

SOFT START

The ADP5302 has an internal soft start function that ramps up

the output voltage in a controlled manner upon startup, thereby

limiting the inrush current. This control prevents possible input

voltage drops when a battery or a high impedance power source

is connected to the input of the device. The typical default soft

start time for the regulator is 350 μs.

A different soft start time (2800 μs) can be programmed for the

ADP5302 via the factory fuse.

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5302 include a precharged start-up

feature to protect the low-side MOSFET from damage during

startup. If the output voltage is precharged before the regulator

turns on, the regulator prevents reverse inductor current—

which discharges the output capacitor—until the internal soft

start reference voltage exceeds the precharged voltage on the

feedback pin.

100% DUTY OPERATION

When the input voltage approaches the output voltage, the

ADP5302 stops switching and enters 100% duty cycle operation.

The device connects the output via the inductor and the internal

high-side power switch to the input. When the input voltage is

charged again and the required duty cycle falls to 95% (typical), the

buck regulator immediately restarts switching and regulation

without allowing overshoot on the output voltage. In hysteresis

mode, the ADP5302 draws an ultralow quiescent current of only

640 nA (typical) during 100% duty cycle operation.

ACTIVE DISCHARGE

The regulator in the ADP5302 integrates an optional, factory

programmable discharge switch from the switching node to

ground. This switch turns on when its associated regulator is

disabled, which helps discharge the output capacitor quickly.

The typical value of the discharge switch is 290 Ω for the

regulator.

By default, the discharge function is not enabled. The active

discharge function can be enabled by the factory fuse.

VINOK FUNCTION

The ADP5302 includes an open-drain VINOK output that

indicates the battery voltage status. The VINOK output becomes

active high when the input voltage on the PVIN pin is above

the reference threshold. When the input voltage falls below the

reference threshold, the VINOK pin goes low. Note that a relatively

typical long validation time 130 μs exists for the status of the

VINOK output to change due to the ultralow power comparator

design.

Different VINOK thresholds can be factory programmable

from 2.05 V to 5.15 V in 50 mV steps. To order a device with

options other than the default options, contact your local

Analog Devices sales or distribution representative.