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ADIN1300BCPZ-R7 数据表(PDF) 60 Page - Analog Devices

部件名 ADIN1300BCPZ-R7
功能描述  Robust, Industrial, Low Latency and Low Power 10 Mbps
PDF  79 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADIN1300BCPZ-R7 数据表(HTML) 60 Page - Analog Devices

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ADIN1300
Data Sheet
Rev. 0 | Page 60 of 79
Bits
Bit Name
Description
Reset
Access
9
TX_LPI
Transmit LPI Bit.
0x0
R
1: transmit PCS is currently receiving LPI.
0: PCS is not currently receiving LPI.
8
RX_LPI
Receive LPI Bit.
0x0
R
1: receive PCS is currently receiving LPI.
0: PCS is not currently receiving LPI.
7
RESERVED
Reserved.
0x0
R
6
TX_MII_CLK_STOP_CPBL
The transmit MII clock stop capable bit always reads as 1'b1.
0x1
R
1: the MAC may stop the clock during LPI.
0: clock not stoppable.
[5:0]
RESERVED
Reserved.
0x0
R
Frame Checker Enable Register
Address: 0x9403, Reset: 0x0001, Name: FC_EN
This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the
PHY (see the FC_TX_SEL register, Address 0x9407, Bit 0) to report the number of frames received, CRC errors, and various other frame
errors. The frame checker frame and error counter registers count these events.
Table 70. Bit Descriptions for FC_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0
R
0
FC_EN
When set, this bit enables the frame checker.
0x1
R/W
Frame Checker Interrupt Enable Register
Address: 0x9406, Reset: 0x0001, Name: FC_IRQ_EN
This register is used to enable the frame checker interrupt. An interrupt is generated when a receive error occurs. Enable the frame
checker/generator interrupt in the interrupt mask register. Set the FC_FG_IRQ_EN bit (IRQ_MASK register, Address 0x0018). The
interrupt status can be read via the FC_FG_IRQ_STAT bit (IRQ_STATUS register, Address 0x0019).
Table 71. Bit Descriptions for FC_IRQ_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0
R
0
FC_IRQ_EN
When set, this bit enables the frame checker interrupt.
0x1
R/W
Frame Checker Transmit Select Register
Address: 0x9407, Reset: 0x0000, Name: FC_TX_SEL
This register is used to select the transmit side or receive side for frames to be checked. If set, frames received on the MAC interface to be
transmitted are checked. The frame checker can be used to verify that correct data is received over the MAC interface and is also useful if
remote loopback is enabled (set the LB_REMOTE_EN bit the in PHY_CTRL_STATUS_1 register, Address 0x0013, Bit 9) because it can
be used to check the received data after it is looped back at the MAC interface.
Table 72. Bit Descriptions for FC_TX_SEL
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0
R
0
FC_TX_SEL
When set, this bit indicates that the frame checker must check frames received to be transmitted
by the PHY.
0x0
R/W
1: check frames from the MAC interface to be transmitted by the PHY.
0: check frames received by the PHY from the remote end.



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