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ADIN1300BCPZ-R7 数据表(PDF) 21 Page - Analog Devices |
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ADIN1300BCPZ-R7 数据表(HTML) 21 Page - Analog Devices |
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21 / 79 page  Data Sheet ADIN1300 Rev. 0 | Page 21 of 79 Note that the GE_SFT_RST_CFG_EN bit is reset to its default value of 0 by this type of reset. The following events occur after a subsystem software reset with pin configuration: • The crystal oscillator circuit is not disabled during this type of reset. • The hardware configuration pins are read and the values latched. These set the default values of the pin dependent registers in the subsystem and PHY core registers. • The MAC interface block is reset. • The PHY core is reset. • The PHY core CMU is reset. • The output reference clock is not available on the CLK25_REF pin during this reset. • If a 125 MHz clock is selected as the PHY output clock it is not available on the GP_CLK pin during this reset. Subsystem Software Reset The subsystem can be reset by setting the GE_SFT_RST bit, Address 0xFF0C to 1. This bit is self clearing. Setting this bit resets the subsystem and PHY core registers, the MAC interface block, and the PHY core. The hardware configuration pins are not reread, and previously latched values of the hardware configuration pins are used to set the default values of the pin dependent registers in the subsystem and PHY core registers. The following events occur after a subsystem software reset: • The crystal oscillator circuit is not disabled during this type of reset. • The hardware configuration pins are not reread. The pin dependent registers in the subsystem registers and PHY core registers are reset to the default values defined by the previously latched values of the hardware configuration pins. • The MAC interface block is reset. • The PHY core is reset. • If a 125 MHz clock is selected as the PHY output clock, the GP_CLK pin, the PHY core CMU is not reset. Otherwise, the CMU is reset. • The output reference clock (if enabled) is available on the CLK25_REF pin during this reset. • The selected PHY output clock (if enabled) is available on the GP_CLK pin during this reset. PHY Core Software Reset The PHY core registers can be reset by setting the SFT_RST bit in the MII_CONTROL register, Address 0x0000 to 1. This bit is self clearing. Setting this bit resets the PHY core registers, the MAC interface block, and the PHY core. The hardware configuration pins are not reread, and previously latched values of the hardware configuration pins are used to set the default values of the pin dependent registers in the PHY core registers. The subsystem registers are not reset to default values. This is a useful way to reset the PHY core registers to a known configuration defined by software without resetting the rest of the ADIN1300 circuitry. The following events occur after a PHY core software reset: • The crystal oscillator circuit is not disabled during this type of reset. • The hardware configuration pins are not reread. The pin dependent registers in PHY core registers are reset to the default values defined by the previously latched values of the hardware configuration pins. The subsystem registers are not reset to their default values. • The MAC interface block is not reset. • The PHY core is reset. • If a 125 MHz clock is selected as the PHY output clock, the GP_CLK pin, the PHY core CMU is not reset. Otherwise, the CMU is reset. • The reference clock (if enabled) is available on the CLK25_REF pin during this reset. • The selected PHY output clock (if enabled) is available on the GP_CLK pin during this reset. Table 18. ADIN1300 Reset Options Summary Reset Type Hardware Pin Configuration Values Latched Following Reset Subsystem Registers Reset PHY Core Registers Reset MAC Interface Block Reset XTAL Oscillator Disabled During Reset CLK25_REF (if Enabled) Available During Reset GP_CLK Output (if Enabled) Available During Reset 1 Hardware Reset Yes Yes Yes Yes Yes No No 2 Subsystem Software Reset with Pin Configuration Yes Yes Yes Yes No No No 3 Subsystem Software Reset No Yes Yes Yes No Yes Yes 5 PHY Core Software Reset No No Yes No No Yes Yes |
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