USB7252SLASHKDX datasheet(36/65 Pages) MICROCHIP

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USB7252

DS00002736D-page 36

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2018 - 2020 Microchip Technology Inc.

7.2

SMBus/I2C Master/Slave Interfaces

The device provides two independent SMBus/I2C controllers (Slave, and Master) which can be used to access internal

device run time registers or program the internal OTP memory. The device contains two 128 byte buffers to enable

simultaneous master/slave operation and to minimize firmware overhead in processed I2C packets. The I2C interfaces

support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.

The SMBus/I2C interfaces are assigned to programmable pins (

PFx) and therefore the device must be programmed into

specific configurations to enable specific interfaces. Refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1])

for additional information.

7.3

I2S Interface

The device provides an integrated I2S interface to facilitate the connection of digital audio devices. The I2S interface

conforms to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus Specification, and

consists of the following signals:

•

I2S_SDI: Serial Data Input

•

I2S_SDO: Serial Data Output

•

I2S_SCK: Serial Clock

•

I2S_LRCK: Left/Right Clock (SS/FSYNC)

•

I2S_MCLK: Master Clock

•

MIC_DET: Microphone Plug Detect

Each audio connection is half-duplex, so

I2S_SDO exists only on the transmit side and I2S_SDI exists only on the

receive side of the interface. Some codecs refer to the Serial Clock (

I2S_SCK) as Baud/Bit Clock (BCLK). Also, the Left/

Right Clock is commonly referred to as LRC or LRCK. The I2S and other audio protocols refer to LRC as Word Select

(WS).

The following codec is supported by default:

• Analog Devices ADAU1961 (24-bit 96KHz)

The I2S interface is assigned to programmable pins (

PFx) and therefore the device must be programmed into specific

configurations to enable the interface. Refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1]) for additional

information.

7.3.1

MODES OF OPERATION

The USB audio class operates in three ways: Asynchronous, Synchronous and Adaptive. There are also multiple oper-

ating modes, such as hi-res, streaming, etc.. Typically for USB devices, inputs such as microphones are Asynchronous,

and output devices such as speakers are Adaptive. The hardware is set up to handle all three modes of operation. It is

recommended that the following configuration be used: Asynchronous IN; Adaptive OUT; 48Khz streaming mode; Two

channels: 16 bits per channel.

7.3.1.1

Asynchronous IN 48KHz Streaming

In this mode, the codec sampling clock is set to 48Khz based on the local oscillator. This clock is never changed. The

data from the codec is fed into the input FIFO. Since the sampling clock is asynchronous to the host clock, the amount

of data captured in every USB frame will vary. This issue is left for the host to handle. The input FIFO has two markers,

a low water mark (THRESHOLD_LOW_VAL), and a high water mark (THRESHOLD_HIGH_VAL). There are three reg-

isters to determine how much data to send back in each frame. If the amount of data in the FIFO exceeds the high water

mark, then HI_PKT_SIZE worth of data is sent. If the data is between the high and low water mark, the normal MID_P-

KT_SIZE amount of data is sent. If the data is below the low water mark, LO_PKT_SIZE worth of data is sent.

Note:

For SMBus/I2C timing information, refer to Section 9.6.7, SMBus Timing and Section 9.6.8, I2C Timing.

Note:

For I2S timing information, refer to Section 9.6.9, I2S Timing. For detailed information on utilizing the I2S

interface, including support for other codecs, refer to the application note “USB7202/USB725x I2S Opera-

tion”, which can be found on the Microchip USB7252 product page at www.microchip.com/USB7252.

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