USB7252SLASHKDX datasheet(44/65 Pages) MICROCHIP

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USB7252

DS00002736D-page 44

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2018 - 2020 Microchip Technology Inc.

8.12.2

EXTERNAL CHIP RESET (

RESET_N)

A valid hardware reset is defined as assertion of

RESET_N, after all power supplies are within operating range, per the

specifications in Section 9.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its asso-

ciated external circuitry) enters Standby Mode and consumes minimal current.

Assertion of

RESET_N causes the following:

1. The PHY is disabled and the differential pairs will be in a high-impedance state.

2. All transactions immediately terminate; no states are saved.

3. All internal registers return to the default state.

4. The external crystal oscillator is halted.

5. The PLL is halted.

8.12.3

USB BUS RESET

In response to the upstream port signaling a reset to the device, the device performs the following:

1. Sets default address to 0.

2. Sets configuration to Unconfigured.

3. Moves device from suspended to active (if suspended).

4. Complies with the USB Specification for behavior after completion of a reset sequence.

The host then configures the device in accordance with the USB Specification.

Note:

All power supplies must have reached the operating levels mandated in Section 9.2, Operating Condi-

tions**, prior to (or coincident with) the assertion of

RESET_N.

Note:

The device does not propagate the upstream USB reset to downstream devices.

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