USB7252SLASHKDX datasheet(7/65 Pages) MICROCHIP

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2018 - 2020 Microchip Technology Inc.

DS00002736D-page 7

USB7252

The USB7252 can be configured for operation through internal default settings. Custom OEM configurations are sup-

ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow

for maximum operational flexibility and are available as GPIOs for customer specific use.

The USB7252 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An inter-

nal block diagram of the USB7252 in an upstream Type-C application is shown in Figure 2-1.

FIGURE 2-1:

USB7252 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION

Note:

All port numbering in this document is LOGICAL port numbering with the device in the default configuration.

LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any

port number remapping or port disabling. The PHYSICAL port number is the port number with respect to

the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by

LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port num-

bering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Config-

uration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL

mapping and additional configuration details.

Hub Controller Logic

2C/SPI

25 Mhz

USB3 USB2

PHY0

+3.3 V

VCORE

PHY5

PHY2

PHY5

PHY1

PHY2

PHY1

PHY3

PHY4

PHY3

PHY0

Hub Feature Controller

GPIO SMB

OTP

SPI

I2S

UART

Mux

HFC

PHY

2C from Master

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