ADP7112

Data Sheet

Rev. D | Page 16 of 21

NOISE REDUCTION OF THE ADP7112 IN

ADJUSTABLE MODE

The ultralow output noise of the ADP7112 is achieved by

keeping the LDO error amplifier in unity gain and setting the

reference voltage equal to the output voltage. This architecture

does not work for an adjustable output voltage LDO in the

conventional sense. However, the ADP7112 architecture allows

any fixed output voltage to be set to a higher voltage with an

external voltage divider. For example, a fixed 5 V output can be

set to a 6 V output according to Equation 3 (see Figure 2).

The disadvantage in using the ADP7112 in this manner is that

the output voltage noise is proportional to the output voltage.

Therefore, it is best to choose a fixed output voltage that is close

to the target voltage to minimize the increase in output noise.

The adjustable LDO circuit can be modified to reduce the

output voltage noise to levels close to that of the fixed output

ADP7112. The circuit shown in Figure 48 adds two additional

the error amplifier is approximately 0.1 dB to 0.8 dB. The actual

This gain ensures that the error amplifier always operates at

slightly greater than unity gain.

at a frequency between 1 Hz and 50 Hz. This setting places the

frequency where the ac gain of the error amplifier is 3 dB down

from the dc gain.

VOUT

VIN

GND

SENSE/ADJ

EN

100kΩ

200kΩ

2.2µF

2.2µF

ON

OFF

10kΩ

R2

100kΩ

+

+

R1

100kΩ

1µF

+

Figure 48. Noise Reduction Modification

The noise of the adjustable LDO is found by using the

following formula, assuming the noise of a fixed output LDO is

approximately 11 μV.

(9)

Based on the component values shown in Figure 48, the

ADP7112 has the following characteristics:



DC gain of 2 (6 dB)



3 dB roll-off frequency of 1.59 Hz



High frequency ac gain of 1.09 (0.75 dB)



Noise reduction factor of 1.83 (5.25 dB)



RMS noise of the adjustable LDO without noise reduction

of 22 μV rms



RMS noise of the adjustable LDO with noise reduction

(assuming 11 μV rms for fixed voltage option) of 12 μV rms

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7112 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP7112 is designed to current limit when the

output load reaches 360 mA (typical). When the output load

exceeds 360 mA, the output voltage is reduced to maintain a

constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts

to rise above 150°C, the output is turned off, reducing the

output current to zero. When the junction temperature drops

below 135°C, the output is turned on again, and output current

is restored to the operating value.

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP7112 current limits, so that only 360

mA is conducted into the short. If self heating of the junction

is great enough to cause the temperature to rise above 150°C,

thermal shutdown activates, turning off the output and reducing

the output current to zero. As the junction temperature cools

and drops below 135°C, the output turns on and conducts

360 mA into the short, again causing the junction

temperature to rise above 150°C. This thermal oscillation

between 135°C and 150°C causes a current oscillation

between 360 mA and 0 mA that continues as long as the short

remains at the output.

Current-limit and thermal limit protections protect the device

against accidental overload conditions. For reliable operation,

device power dissipation must be externally limited so that the

junction temperature does not exceed 125°C.

EFFECT OF NOISE REDUCTION ON START-UP TIME

The start-up time of the ADP7112 is affected by the noise

reduction network and must be considered in applications

where power supply sequencing is critical.

The noise reduction circuit adds a pole in the feedback loop,

slowing down the start-up time. The start-up time for an

adjustable model with a noise reduction network can be

approximated using the following equation:

as shown in Figure 48, the start-up time is approximately 0.6 sec.

length of the start-up time instead of the soft start capacitor.