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PCF8536AT 数据表(PDF) 36 Page - NXP Semiconductors

部件名 PCF8536AT
功能描述  Automotive 40 횞 4 LCD driver
PDF  54 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8536AT 数据表(HTML) 36 Page - NXP Semiconductors

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PCA8576F
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 3 December 2014
36 of 54
NXP Semiconductors
PCA8576F
Automotive 40 × 4 LCD driver
13. Dynamic characteristics
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
Not tested in production.
Table 21.
Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
fclk(int)
internal clock frequency
[1] 3505
4800
6240
Hz
fclk(ext)
external clock frequency
960
-
6720
Hz
ffr
frame frequency
internal clock
146
200
260
Hz
external clock
40
-
280
Hz
tclk(H)
HIGH-level clock time
60
-
-
s
tclk(L)
LOW-level clock time
60
-
-
s
Synchronization
tPD(SYNC_N) SYNC propagation delay
-
30
-
ns
tSYNC_NL
SYNC LOW time
1
-
-
s
tPD(drv)
driver propagation delay
VLCD = 5 V
[2] --
30
s
I2C-bus[3]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL
clock
1.3
-
-
s
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
Pin SDA
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pins SCL and SDA
tBUF
bus free time between a
STOP and START
condition
1.3
-
-
s
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tr
rise time of both SDA and
SCL signals
fSCL = 400 kHz
-
-
0.3
s
fSCL < 125 kHz
-
-
1.0
s
tf
fall time of both SDA and
SCL signals
--
0.3
s
Cb
capacitive load for each
bus line
--
400
pF
tw(spike)
spike pulse width
on the I2C-bus
-
-
50
ns



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