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ADP1764ACPZ-R7 数据表(PDF) 14 Page - Analog Devices

部件名 ADP1764ACPZ-R7
功能描述  4 A, Low VIN, Low Noise, CMOS Linear Regulator
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1764ACPZ-R7 数据表(HTML) 14 Page - Analog Devices

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ADP1764
Data Sheet
Rev. A | Page 14 of 20
ADJUSTABLE OUTPUT VOLTAGE
The output voltage of the ADP1764 can be set over a 0.5 V to
1.5 V range. Connect a resistor (RADJ) from the VADJ pin to
ground to set the output voltage. To calculate the output voltage
(VOUT), use the following equation:
VOUT = AD × (RADJ × IADJ)
(3)
where:
AD is the gain factor with a typical value of 2.99 between the
VADJ pin and VOUT pin.
IADJ is the 50 μA constant current out of the VADJ pin.
ENABLE FEATURE
The ADP1764 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in Figure 42,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
CH1 200mV
CH2 200mV
10.00ms
100kSPS
10k POINTS
CH1
1.21V
T
121.9200ms
2
1
T
EN
VOUT
Figure 42. Typical EN Pin Operation
As shown in Figure 43, the EN pin has built in hysteresis. This
hysteresis prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
1.4
0
0.59
0.66
EN THRESHOLD (V)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
0.60
0.61
0.62
0.63
0.64
0.65
TA = +125°C
TA = +85°C
TA = +25°C
TA = 0°C
TA = –40°C
Figure 43. Output Voltage vs. EN Threshold, VOUT = 1.3 V
POWER-GOOD (PG) FEATURE
The ADP1764 provides a power-good pin (PG) to indicate the
status of the output. This open-drain output requires an external
pull-up resistor that can be connected to VIN or VOUT. If the
device is in shutdown mode, current-limit mode, or thermal
shutdown, or if it falls below 90% of the nominal output voltage,
PG immediately transitions low. During soft start, the rising
threshold of the power-good signal is 96.5% of the nominal
output voltage.
The open-drain output is held low when the ADP1764 has
sufficient input voltage to turn on the internal PG transistor. An
optional soft start delay can be detected. The PG transistor is
terminated via a pull-up resistor to VIN or VOUT.
Power-good accuracy is 93.8% of the nominal regulator output
voltage when this voltage is rising, with a 96.5% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no good if VOUT falls below 93.8%.
A normal power-down triggers a power good when VOUT is
at 96.5%.
CH1 1V
CH2 1V
CH3 1V
200µs
5.00MSPS
10k POINTS
CH2
1.30V
T
–70.00000µs
2
3
1
T
EN
PG
VOUT
Figure 44. VOUT vs. Typical PG Voltage Behavior, VIN Rising (VOUT = 1.3 V)
CH1 1V BW
CH2 1V BW
CH3 1V BW
200µs
500MSPS
1M POINTS
CH2
700mV
T
–5.20000µs
2
3
1
T
EN
PG
VOUT
Figure 45. VOUT vs. Typical PG Voltage Behavior, VIN Falling (VOUT = 1.3 V)



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