STM8L151C2 datasheet(17/123 Pages) STMICROELECTRONICS

17 / 123 page

DS7204 Rev 11

17/123

STM8L151x2, STM8L151x3

Functional overview

3.3

Reset and supply management

3.3.1

Power supply scheme

The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power

supply pins must be connected as follows:

•

VSS1; VDD1 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for

I/Os and for the internal regulator. Provided externally through VDD1 pins, the

corresponding ground pin is VSS1.

•

VSSA; VDDA = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for

analog peripherals (minimum voltage to be applied to VDDA is 1.8 V when the ADC1 is

used). VDDA and VSSA must be connected to VDD1 and VSS1, respectively.

•

VSS2; VDD2 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for

I/Os. VDD2 and VSS2 must be connected to VDD1 and VSS1, respectively.

•

VREF+; VREF- (for ADC1): external reference voltage for ADC1. Must be provided

externally through VREF+ and VREF- pin.

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,

and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,

the option byte loading process starts, either to confirm or modify default thresholds, or to

disable BOR permanently (in which case, the VDD min value at power down is 1.65 V).

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Halt mode, it is possible to automatically switch off the

internal reference voltage (and consequently the BOR) in Halt mode. The device remains

under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need

for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when

VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3

Voltage regulator

The low-density STM8L151x2/3 embeds an internal voltage regulator for generating the 1.8

V power supply for the core and peripherals.

This regulator has two different modes:

•

Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes.

•

Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and

Low power wait modes.

When entering Halt or Active-halt modes, the system automatically switches from the MVR

to the LPVR in order to reduce current consumption.

STM8L151C2 数据表(PDF) 17 Page - STMicroelectronics

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