ADE7932 datasheet(91/125 Pages) AD

91 / 125 page

Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 91 of 125

6. Enable the data memory RAM protection by writing 0xAD

to the internal 8-bit register located at Address 0xE7FE,

followed by a write of 0x80 to the internal 8-bit register

located at Address 0xE7E3.

7. Start the DSP by writing 0x0001 to the run register

(Address 0xE228).

BIT STREAM COMMUNICATION BETWEEN THE

ADE7978 AND THE ADE7933/ADE7932 AND

ADE7923

The ADE7978 extracts information from the ADE7933/

ADE7932 and ADE7923 devices of the system using the bit

stream communication shown in Figure 115. The ADE7978

generates a 1.024 MHz clock signal at the SYNC pin. This clock

signal is equal to 1/16 of the ADE7978 internal clock, CLKIN

(CLKIN/16 = 1.024 MHz for XTALIN = 16.384 MHz) and one-

fourth of the ADE7933/ADE7932 and ADE7923 XTAL1 clock

(CLKIN/4). The duty cycle of this clock is 25%.

The low to high transition of SYNC is generated one-fourth of

a cycle before a high to low transition of the CLKIN/4 clock.

SYNC stays high for one CLKIN/4 cycle and stays low for the

rest of the period.

After the first high to low transition of SYNC, the ADE7978

CLKIN/4 transitions from high to low four times. At each high

to low transition of CLKIN/4, the ADE7933/ADE7932 and

ADE7923 devices place these bits on the DATA pin: the bits

coming from the first stage of the ADCs and the bits of the

temperature offset stored in the ADE7933/ADE7932 and

ADE7923 devices. The order of the bits on the Phase A

ADE7933/ADE7932 is VA bit, VA2 bit, temperature offset bit,

and IA bit. The other ADE7933/ADE7932 and ADE7923

devices follow the same pattern. The ADE7978 receives these

bits at its DATA_A, DATA_B, DATA_C, and DATA_N pins. The

process is repeated when a new high to low transition takes place

on SYNC. The delimiters identifying the 8-bit signed number

representing the temperature offset are shown in Figure 116.

Within the frame, the temperature offset is sent out by the

ADE7933/ADE7932 and ADE7923 with the less significant

bit first.

The delimiters identifying the 8-bit signed number representing

the temperature offset are shown in Figure 116. Within the frame,

the temperature offset is sent out by the ADE7933/ADE7932

and ADE7923 with the less significant bit first.

Any master device that can generate a 1.024 MHz SYNC signal

like the one shown in Figure 115 and can filter the bit streams

coming from the DATA pins of the ADE7933/ADE7932 and

ADE7923 devices can replace the ADE7978.

ADE7978

CLKIN/4

SYNC

DATA_A

DATA_B

DATA_C

DATA_N

VA BIT

VA2 BIT

TEMP

OFFSET

VB BIT

VB2 BIT

TEMP

OFFSET

VC BIT

VC2 BIT

TEMP

OFFSET

VN1 BIT

VN2 BIT

TEMP

OFFSET

IA BIT

IB BIT

IC BIT

IN BIT

VA BIT

VB BIT

VC BIT

VN1 BIT

Figure 115. Bit Stream Communication Between the ADE7978 and the ADE7933/ADE7932 Devices

BIT7

BIT6

BIT5

BIT4

4 LEAST SIGNIFICANT

BITS OF TEMPERATURE

OFFSET

BIT3

BIT2

BIT1

BIT0

4 MOST SIGNIFICANT

BITS OF TEMPERATURE

OFFSET

EARLIEST BIT OF

THE FRAME

LAST BIT OF

THE FRAME

Figure 116. Temperature Offset Bit Stream Communication

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