ADE7932 datasheet(97/125 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 97 of 125

SERIAL INTERFACES

The ADE7978 has three serial port interfaces: one fully licensed

I2C interface, one serial peripheral interface (SPI), and one high

speed data capture (HSDC) port. The SPI pins are multiplexed

with pins for the I2C and HSDC ports; therefore, the ADE7978

accepts two configurations: one using the SPI port only and one

using the I2C port in conjunction with the HSDC port.

SERIAL INTERFACE SELECTION

After a reset of the ADE7978, the HSDC port is always disabled.

After power-up or after a hardware reset, select the I2C or SPI

port by manipulating the SS/HSA pin (Pin 16).

•

If the SS/HSA pin is pulled high, the ADE7978 uses the I2C

port until another hardware reset is executed.

•

If the SS/HSA pin is toggled high to low three times, the

ADE7978 uses the SPI port until another hardware reset is

executed.

The manipulation of the SS/HSA pin can be accomplished in

two ways.

•

Use the SS pin of the master device (that is, the micro-

controller) as a regular I/O pin and toggle it three times.

•

Execute three SPI write operations to a location in the

address space that is not allocated to a specific ADE7978

registers can be executed). These writes cause the SS/HSA

pin to toggle three times. For more information about the

write protocol involved, see the SPI Write Operation section.

After the serial port selection is completed, the selection must

be locked. In this way, the active port remains enabled until a

hardware reset or a power-down operation is performed. If the

active serial port is I2C, Bit 0 (I2C_LOCK) of the CONFIG2

the write to this bit is done, the ADE7978 ignores spurious

toggling of the SS/HSA pin, and a switch to the SPI port is no

longer possible. If the active serial port is SPI, any write to the

CONFIG2 register locks the port. After this write, a switch to

the I2C port is no longer possible.

The functionality of the ADE7978 is configurable via several

on-chip registers. The contents of these registers can be updated

or read using the I2C or SPI interface. The HSDC port provides

the state of up to 16 registers that contain the instantaneous

values of phase voltages and neutral currents, as well as active,

reactive, and apparent powers.

COMMUNICATION VERIFICATION

The ADE7978 includes a set of three registers that allow any

communication via I2C or SPI to be verified. The LAST_OP

(Address 0xEA01), LAST_ADD (Address 0xE9FE), and LAST_

RWDATA registers record the nature, address, and data of the

last successful communication, respectively. The LAST_RWDATA

the successful communication (see Table 37).

Table 37. LAST_RWDATA Register Locations

Communication Type

Address

8-Bit Read/Write

0xE7FD

16-Bit Read/Write

0xE9FF

32-Bit Read/Write

0xE5FF

After each successful communication with the ADE7978, the

address of the register that was last accessed is stored in the

16-bit LAST_ADD register (Address 0xE9FE). This read-only

operation is completed.

The LAST_OP register (Address 0xEA01) stores the nature of

the operation; that is, it indicates whether a read or a write was

performed. If the last operation was a write, the LAST_OP

the LAST_OP register stores the value 0x35. The LAST_RWDATA

An unsuccessful read or write operation is not stored in these

registers.

When the LAST_OP, LAST_ADD, and LAST_RWDATA

registers are read, their values remain unchanged.

I2C-COMPATIBLE INTERFACE

The ADE7978 supports a fully licensed I2C interface. The I2C

interface is implemented as a full hardware slave. The maximum

serial clock frequency supported by the I2C interface is 400 kHz.

SDA is the data I/O pin, and SCL is the serial clock. These two

pins are shared with the MOSI and SCLK pins of the on-chip SPI

interface. The SDA and SCL pins are configured in a wire-AND

format that allows arbitration in a multimaster system.

The transfer sequence of an I2C system consists of a master

device initiating a transfer by generating a start condition while

the bus is idle. The master transmits the address of the slave

device and the direction of the data transfer in the initial

address transfer. If the slave acknowledges the master, the data

transfer is initiated. Data transfer continues until the master

issues a stop condition, and the bus becomes idle.

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