USB7006SLASHKDX datasheet(41/56 Pages) MICROCHIP

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DS00003715B-page 41

USB7006

9.6

AC Specifications

This section details the various AC timing specifications of the device.

9.6.1

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after or

at the same time as VCORE. Similarly, RESET_N should rise after or at the same time as VDD33.

Note:

In a typical application, voltage may be present on the VBUS_DET pin before the device is powered. This

is permissible as this pin is designed specifically for this scenario.

9.6.2

POWER-ON AND CONFIGURATION STRAP TIMING

Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where

RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following

timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in

Section 9.2, Operating Conditions**.

Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, Reset and Con-

figuration Strap Timing for additional details.

FIGURE 9-2:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

TABLE 9-4:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Symbol

Description

Min

Typ

Max

Units

tVDD33

VDD33 to VCORE rise delay

treset

VDD33 to RESET_N rise delay

FIGURE 9-3:

POWER-ON CONFIGURATION STRAP VALID TIMING

TABLE 9-5:

POWER-ON CONFIGURATION STRAP LATCHING TIMING

Symbol

Description

Min

Typ

Max

Units

tcsh

Configuration strap hold after external power supplies at opera-

tional levels

1ms

VDD33

VCORE

RESET_N

All External

Power Supplies

Vopp

Configuration

Straps

tcsh

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