USB7006SLASHKDX datasheet(42/56 Pages) MICROCHIP

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USB7006

DS00003715B-page 42

 2022 Microchip Technology Inc. and its subsidiaries

9.6.3

RESET AND CONFIGURATION STRAP TIMING

Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of

RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to

Section 8.9, Resets for additional information on resets. Refer to Section 3.3, Configuration Straps and Programmable

Functions for additional information on configuration straps.

9.6.4

POWER-ON OR RESET TO SMBUS SLAVE READY TIMING

Figure 9-5 illustrates the SMBus Slave interface readiness in relation to power-on or de-assertion of RESET_N. In order

to ensure reliable SMBus slave operation, the SMBus master must allow the bus to remain idle until tSMBUS_RDY timing

has been met. The operational levels (Vopp) for the external power supplies are detailed in Section 9.2, Operating Con-

ditions**.

FIGURE 9-4:

RESET_N CONFIGURATION STRAP TIMING

TABLE 9-6:

RESET_N CONFIGURATION STRAP TIMING

Symbol

Description

Min

Typ

Max

Units

trstia

RESET_N input assertion time

tcsh

Configuration strap pins hold after RESET_N deassertion

Note:

The clock input must be stable prior to RESET_N deassertion.

Configuration strap latching and output drive timings shown assume that the Power-On reset has finished

first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply.

FIGURE 9-5:

POWER-ON OR RESET TO SMBUS SLAVE READY TIMING

TABLE 9-7:

POWER-ON OR RESET TO SMBUS SLAVE READY TIMING

Symbol

Description

Min

Typ

Max

Units

tSMBUS_RDY Power-on or RESET_N deassertion to SMBus ready

100

RESET_N

Configuration

Straps

trstia

tcsh

All External

Power Supplies

& Reset

Vopp

SMBus

SMBus commands accepted

(if SMBus slave inter face is enabled)

SMBus interface not available

(slave interface will stretch clock if addressed)

Power-on-Reset

SOC_CFG STAGE

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