USB7006SLASHKDX datasheet(11/56 Pages) MICROCHIP

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DS00003715B-page 11

USB7006

Downstream

Ports 1-6 USB

2.0 D+

USB2DN_DP[1:6]

I/O-U

Downstream USB 2.0 Ports 1-6 Data Plus

(D+).

Connect

directly to

3.3V

Downstream

Ports 1-6 USB

2.0 D-

USB2DN_DM[1:6]

I/O-U

Downstream USB 2.0 Ports 1-6 Data Minus

(D-)

Connect

directly to

3.3V

VBUS Detect

VBUS_DET

This signal detects the state of the upstream

bus power.

Externally, VBUS can be as high as 5.5 V,

which can be damaging to this pin. The

amplitude of VBUS must be reduced by a

voltage divider. The recommended voltage

divider is shown below.

For self-powered applications with a perma-

nently attached host, this pin must be con-

nected to either 3.3 V or 5.0 V through a

resistor divider to provide 3.3 V.

In embedded applications, VBUS_DET may

be controlled (toggled) when the host

desires to renegotiate a connection without

requiring a full reset of the device.

Not

Recom-

mended.

If unused,

tie to a

3.3V rail

through a

10-100k

pull-up

resistor.

SPI Interface

SPI Clock

SPI_CLK

I/O-U

SPI clock. This pin should have a weak pull-

down resistor connected at all times to

ensure the pin stays low during reset.

Weak pull-

down to

GND

SPI Data 3-0

SPI_D[3:0]

I/O-U

SPI Data 3-0. If the SPI interface is enabled,

these signals function as Data 3 through 0.

Note 3-1

SPI_D0 operates as the

CFG_BC_EN

s trap if

external SPI memory is not

used. It must be terminated

with the selected strap

resistor to 3.3V or GND.

SPI_D[1:3] s hould be

connected to GND through

a weak pull-down.

Note 3-1

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

If Unused

VBUS_UP

43K

VBUS_DET

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